Patents by Inventor Masayuki Sakakura

Masayuki Sakakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10115831
    Abstract: In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Ryosuke Watanabe, Junichiro Sakata, Kengo Akimoto, Akiharu Miyanaga, Takuya Hirohashi, Hideyuki Kishida
  • Publication number: 20180308558
    Abstract: A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: Masayuki SAKAKURA, Yuugo GOTO, Hiroyuki MIYAKE, Daisuke KUROSAKI
  • Patent number: 10109744
    Abstract: It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: October 23, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinari Higaki, Masayuki Sakakura, Shunpei Yamazaki
  • Patent number: 10103270
    Abstract: It is an object to provide a transistor having a new multigate structure in which operating characteristics and reliability are improved. In a transistor having a multigate structure, which includes two gate electrodes electrically connected to each other and a semiconductor layer including two channel regions connected in series formed between a source region and a drain region, and a high concentration impurity region is formed between the two channel regions; the channel length of the channel region adjacent to the source region is longer than the channel length of the channel region adjacent to the drain region.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: October 16, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Shunpei Yamazaki
  • Publication number: 20180286887
    Abstract: An object of the present invention is to decrease substantial resistance of an electrode such as a transparent electrode or a wiring, and furthermore, to provide a display device for which is possible to apply same voltage to light-emitting elements. In the invention, a auxiliary wiring that is formed in one layer in which a conductive film of a semiconductor element such as an electrode, wiring, a signal line, a scanning line, or a power supply line is connected to an electrode typified by a second electrode, and a wiring. It is preferable that the auxiliary wiring is formed into a conductive film to include low resistive material, especially, formed to include lower resistive material than the resistance of an electrode and a wiring that is required to reduce the resistance.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Inventors: Noriko Miyagi, Masayuki Sakakura, Tatsuya Arao, Ritsuko Nagao, Yoshifumi Tanada
  • Publication number: 20180233601
    Abstract: A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.
    Type: Application
    Filed: April 13, 2018
    Publication date: August 16, 2018
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA
  • Publication number: 20180226510
    Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Ryosuke WATANABE, Junichiro SAKATA, Kengo AKIMOTO, Akiharu MIYANAGA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Patent number: 10035386
    Abstract: To provide a circuit with low power consumption, a semiconductor device with low power consumption, a highly reliable semiconductor device, a tire whose performance is controlled, a moving object whose performance is controlled, or a moving object with a high degree of safety. A tire provided with a semiconductor device is provided. The semiconductor device includes a circuit portion, an antenna, and a sensor element. The circuit portion includes a transistor. The transistor includes an oxide semiconductor. The sensor element is configured to measure the air pressure of the tire.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 31, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Masayuki Sakakura, Kazuaki Ohshima
  • Publication number: 20180204988
    Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.
    Type: Application
    Filed: March 13, 2018
    Publication date: July 19, 2018
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kaoru Tsuchiya, Aya Anzai, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda
  • Patent number: 10014068
    Abstract: A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: July 3, 2018
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masayuki Sakakura, Yuugo Goto, Hiroyuki Miyake, Daisuke Kurosaki
  • Patent number: 9997542
    Abstract: An object of the present invention is to decrease substantial resistance of an electrode such as a transparent electrode or a wiring, and furthermore, to provide a display device for which is possible to apply same voltage to light-emitting elements. In the invention, a auxiliary wiring that is formed in one layer in which a conductive film of a semiconductor element such as an electrode, wiring, a signal line, a scanning line, or a power supply line is connected to an electrode typified by a second electrode, and a wiring. It is preferable that the auxiliary wiring is formed into a conductive film to include low resistive material, especially, formed to include lower resistive material than the resistance of an electrode and a wiring that is required to reduce the resistance.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 12, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Noriko Miyagi, Masayuki Sakakura, Tatsuya Arao, Ritsuko Nagao, Yoshifumi Tanada
  • Publication number: 20180158961
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 7, 2018
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Hideomi SUZAWA
  • Patent number: 9991290
    Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: June 5, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Hideto Ohnuma, Hideaki Kuwabara
  • Publication number: 20180151748
    Abstract: It is an object to provide a transistor having a new multigate structure in which operating characteristics and reliability are improved. In a transistor having a multigate structure, which includes two gate electrodes electrically connected to each other and a semiconductor layer including two channel regions connected in series formed between a source region and a drain region, and a high concentration impurity region is formed between the two channel regions; the channel length of the channel region adjacent to the source region is longer than the channel length of the channel region adjacent to the drain region.
    Type: Application
    Filed: January 29, 2018
    Publication date: May 31, 2018
    Inventors: Masayuki SAKAKURA, Shunpei YAMAZAKI
  • Patent number: 9972646
    Abstract: An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 15, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Shunpei Yamazaki
  • Publication number: 20180130911
    Abstract: It is an object of the present invention to provide a method for manufacturing a display device in which unevenness generated under a light-emitting element does not impart an adverse effect on the light-emitting element. It is another object of the invention to provide a method for manufacturing a display device in which penetration of water into the inside of the display device through a film having high moisture permeability can be suppressed without increasing processing steps considerably. A display device of the present invention comprises a thin film transistor and a light-emitting element, the light-emitting element including a light-emitting laminated body interposed between a first electrode and a second electrode; wherein the first electrode is formed over an insulating film formed over the thin film transistor; and wherein a planarizing film is formed in response to the first electrode between the first electrode and the insulating film.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 10, 2018
    Inventors: Masayuki SAKAKURA, Shunpei YAMAZAKI
  • Publication number: 20180129831
    Abstract: To provide an authentication system and a semiconductor device utilizing the system. The semiconductor device includes a transmission/reception circuit, a control circuit, an analog-to-digital converter circuit, a memory device, and a fingerprint sensor. At least one of the control circuit, the analog-to-digital converter circuit, and the memory device includes a transistor including an oxide semiconductor in a channel formation region. The control circuit has a function of receiving an instruction signal from the outside of the semiconductor device through the transmission/reception circuit. The memory device has fingerprint data for comparison and confidential information. The control circuit has a function of comparing fingerprint data to be compared which is obtained by the fingerprint sensor and the fingerprint data for comparison.
    Type: Application
    Filed: April 11, 2016
    Publication date: May 10, 2018
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomokazu Yokoi, Masayuki Sakakura
  • Publication number: 20180122958
    Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.
    Type: Application
    Filed: December 19, 2017
    Publication date: May 3, 2018
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Ryosuke WATANABE, Junichiro SAKATA, Kengo AKIMOTO, Akiharu MIYANAGA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Patent number: 9954003
    Abstract: A semiconductor device with high design flexibility is provided. A first transistor and a second transistor having electrical characteristics different from those of the first transistor are provided over the same layer without significantly increasing the number of manufacturing steps. For example, semiconductor materials with different electron affinities are used for a semiconductor layer in which a channel of the first transistor is formed and a semiconductor layer in which a channel of the second transistor is formed. This allows the threshold voltages of the first transistor and the second transistor to differ from each other. Forming a gate electrode using a damascene process enables miniaturization and high density of the transistors. Furthermore, a highly-integrated semiconductor device is provided.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinpei Matsuda, Masayuki Sakakura, Yuki Hata, Shuhei Nagatsuka, Yuta Endo, Shunpei Yamazaki
  • Patent number: 9947801
    Abstract: A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: April 17, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura