Abstract: A time series sensor data processing device is provided. The time series sensor data processing device includes: a frame generating unit configured to generate a plurality of frames from time series sensor data acquired from a sensor, each of the frames having a predetermined frame size, the sensor being provided in an apparatus; a time information adding unit configured to add a value indicating corresponding time information to each of the generated frames; and a determining unit configured to determine presence or absence of an abnormality of the apparatus by using a neural network, the neural network learning a combination of each of the plurality of frames and the value indicating the corresponding time information and a combination of a data pattern of each frame stored in advance and predetermined timing.

Abstract: A clock distribution circuit, which is provided in IC that has a first sequential circuit receiving first clock through a first branch node on a first clock network, a second sequential circuit receiving second clock through a second branch node on a second clock network, and a data transfer path between the first and second sequential circuits, includes: a first PLL receiving a first feedback clock that is the first clock branched at the first branch node and outputting the first clock to the first clock network based on the first feedback clock; and a second PLL receiving a second feedback clock that is the second clock branched at the second branch node and outputting the second clock to the second clock network based on the second feedback clock. A branch node is provided at least one of between the first PLL and the first branch node and between the second PLL and the second branch node.

Abstract: A clock distribution circuit, which is provided in IC that has a first sequential circuit receiving first clock through a first branch node on a first clock network, a second sequential circuit receiving second clock through a second branch node on a second clock network, and a data transfer path between the first and second sequential circuits, includes: a first PLL receiving a first feedback clock that is the first clock branched at the first branch node and outputting the first clock to the first clock network based on the first feedback clock; and a second PLL receiving a second feedback clock that is the second clock branched at the second branch node and outputting the second clock to the second clock network based on the second feedback clock. A branch node is provided at least one of between the first PLL and the first branch node and between the second PLL and the second branch node.