Patents by Inventor Masayuki Soutome
Masayuki Soutome has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11107784Abstract: A semiconductor device includes: a multilayer substrate which includes a circuit board and an insulating plate on which the circuit board is formed; and a contact part having a cylindrical hollow hole therein and an open end bonded to a bonding area on the front surface of the circuit board via bonding material. In the case of this semiconductor device, wettability of a contact area of the contact part with respect to the bonding material is approximately equal to wettability of at least the bonding area of the circuit board with respect to the bonding material. Thus, the rising of the bonding material into the hollow hole of the contact part during heating performed when the contact part is bonded to the circuit board is reduced.Type: GrantFiled: February 25, 2020Date of Patent: August 31, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Rikihiro Maruyama, Masaoki Miyakoshi, Masayuki Soutome, Kazuya Adachi, Takeshi Yokoyama
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Patent number: 11107787Abstract: A member for semiconductor device includes a metal portion configured to be bonded to another member by solder, and a treated coating covering a surface of the metal portion, the treated coating including a treatment agent. The treated coating vaporizes at a temperature lower than or equal to a solidus temperature of the solder.Type: GrantFiled: November 8, 2018Date of Patent: August 31, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Shinji Sano, Yoshihiro Kodaira, Masayuki Soutome, Kazunaga Onishi
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Publication number: 20200194392Abstract: A semiconductor device includes: a multilayer substrate which includes a circuit board and an insulating plate on which the circuit board is formed; and a contact part having a cylindrical hollow hole therein and an open end bonded to a bonding area on the front surface of the circuit board via bonding material. In the case of this semiconductor device, wettability of a contact area of the contact part with respect to the bonding material is approximately equal to wettability of at least the bonding area of the circuit board with respect to the bonding material. Thus, the rising of the bonding material into the hollow hole of the contact part during heating performed when the contact part is bonded to the circuit board is reduced.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventors: Rikihiro MARUYAMA, Masaoki MIYAKOSHI, Masayuki SOUTOME, Kazuya ADACHI, Takeshi YOKOYAMA
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Patent number: 10262874Abstract: A semiconductor module radiator plate fabrication method includes soldering a plurality of insulating substrates of different shapes to a flat radiator plate, and forming a convex curve on an insulating substrate side of the radiator plate; obtaining a first concave curve by reversing the convex curve; setting a second concave curve on an insulating substrate side of a radiator plate after soldering, a bottom of the second concave curve being positioned under clearance between the plurality of insulating substrates; adding the first curve and the second curve to calculate a third concave curve on the insulating substrate side; and forming the third curve on a flat plate to form a radiator plate before soldering.Type: GrantFiled: September 26, 2016Date of Patent: April 16, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yoshinori Uezato, Masayuki Soutome, Rikihiro Maruyama, Tomoaki Goto
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Publication number: 20190081020Abstract: A member for semiconductor device includes a metal portion configured to be bonded to another member by solder, and a treated coating covering a surface of the metal portion, the treated coating including a treatment agent. The treated coating vaporizes at a temperature lower than or equal to a solidus temperature of the solder.Type: ApplicationFiled: November 8, 2018Publication date: March 14, 2019Inventors: Shinji SANO, Yoshihiro KODAIRA, Masayuki SOUTOME, Kazunaga ONISHI
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Patent number: 10153246Abstract: There is provided a method for producing a member for semiconductor device which can reduce generation of a large number of voids in a solder-bonded portion without increasing production cost. The method includes the step of preparing a first member including a metal portion capable of being bonded by solder and the step of coating the surface of the metal portion of the first member with a treatment agent to form a treated coating which vaporizes at a temperature lower than or equal to the solidus temperature of the solder.Type: GrantFiled: November 30, 2016Date of Patent: December 11, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Shinji Sano, Yoshihiro Kodaira, Masayuki Soutome, Kazunaga Onishi
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Publication number: 20170207187Abstract: There is provided a method for producing a member for semiconductor device which can reduce generation of a large number of voids in a solder-bonded portion without increasing production cost. The method includes the step of preparing a first member including a metal portion capable of being bonded by solder and the step of coating the surface of the metal portion of the first member with a treatment agent to form a treated coating which vaporizes at a temperature lower than or equal to the solidus temperature of the solder.Type: ApplicationFiled: November 30, 2016Publication date: July 20, 2017Inventors: Shinji SANO, Yoshihiro KODAIRA, Masayuki SOUTOME, Kazunaga ONISHI
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Publication number: 20170011935Abstract: A semiconductor module radiator plate fabrication method includes soldering a plurality of insulating substrates of different shapes to a flat radiator plate, and forming a convex curve on an insulating substrate side of the radiator plate; obtaining a first concave curve by reversing the convex curve; setting a second concave curve on an insulating substrate side of a radiator plate after soldering, a bottom of the second concave curve being positioned under clearance between the plurality of insulating substrates; adding the first curve and the second curve to calculate a third concave curve on the insulating substrate side; and forming the third curve on a flat plate to form a radiator plate before soldering.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoshinori UEZATO, Masayuki SOUTOME, Rikihiro MARUYAMA, Tomoaki GOTO
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Publication number: 20130306296Abstract: When insulating substrates of different shapes are soldered to a radiator plate, a third concave curve is previously formed on an insulating substrate side of the radiator plate. The third curve is determined by adding a second concave curve which is expected at the time of actually soldering the insulating substrates to the radiator plate to a first concave curve obtained by moving upside down a convex curve which appears at the time of soldering the insulating substrates to a flat radiator plate. A bottom of the third curve is positioned under the large insulating substrate, and a curvature of a portion where the distance between the bottom and a reference point of the radiator plate is longer is made smaller than a curvature of a portion where the distance between the bottom and a reference point of the radiator plate is shorter.Type: ApplicationFiled: July 25, 2013Publication date: November 21, 2013Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoshinori Uezato, Masayuki Soutome, Rikihiro Maruyama, Tomoaki Goto
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Publication number: 20120111924Abstract: According to one embodiment of the invention, there is provided a lead-free solder including an alloy rolled into a shape of sheet. The alloy includes: tin; from 10 wt % to less than 25 wt % of silver; and from 3 wt % to 5 wt % of copper. The alloy is free from lead.Type: ApplicationFiled: January 18, 2012Publication date: May 10, 2012Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventors: Kazuyuki MAKITA, Masaki ICHINOSE, Taketo WATASHIMA, Masayuki SOUTOME, Mitsuo YAMASHITA, Takeshi ASAGI, Masatoshi HIRAI, Toru MURATA
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Patent number: 8158458Abstract: A power semiconductor module and a method of manufacture thereof includes lead a frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently.Type: GrantFiled: October 9, 2009Date of Patent: April 17, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Osamu Ikawa, Eiji Mochizuki, Masayuki Soutome, Norio Arikawa
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Patent number: 7723846Abstract: A power semiconductor module and a method of manufacture thereof includes a lead frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently.Type: GrantFiled: September 12, 2005Date of Patent: May 25, 2010Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Osamu Ikawa, Eiji Mochizuki, Masayuki Soutome, Norio Arikawa
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Publication number: 20100055845Abstract: A power semiconductor module and a method of manufacture thereof includes lead a frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently.Type: ApplicationFiled: October 9, 2009Publication date: March 4, 2010Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Osamu IKAWA, Eiji MOCHIZUKI, Masayuki SOUTOME, Norio ARIKAWA
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Publication number: 20090286093Abstract: According to one embodiment of the invention, there is provided a lead-free solder including an alloy rolled into a shape of sheet. The alloy includes: tin; from 10 wt % to less than 25 wt % of silver; and from 3 wt % to 5 wt % of copper. The alloy is free from lead.Type: ApplicationFiled: July 2, 2009Publication date: November 19, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Kazuyuki MAKITA, Masaki Ichinose, Taketo Watashima, Masayuki Soutome, Mitsuo Yamashita, Takeshi Asagi, Masatoshi Hirai, Toru Murata
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Publication number: 20070029678Abstract: According to one embodiment of the invention, there is provided a lead-free solder including an alloy rolled into a shape of sheet. The alloy includes: tin; from 10 wt % to less than 25 wt % of silver; and from 3 wt % to 5 wt % of copper. The alloy is free from lead.Type: ApplicationFiled: August 4, 2006Publication date: February 8, 2007Inventors: Kazuyuki Makita, Masaki Ichinose, Taketo Watashima, Masayuki Soutome, Mitsuo Yamashita, Takeshi Asagi, Masatoshi Hirai, Toru Murata
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Publication number: 20060060982Abstract: A power semiconductor module and a method of manufacture thereof includes lead a frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently.Type: ApplicationFiled: September 12, 2005Publication date: March 23, 2006Applicant: Fuji Electric Device Technology Co., Ltd.Inventors: Osamu Ikawa, Eiji Mochizuki, Masayuki Soutome, Norio Arikawa
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Patent number: D587662Type: GrantFiled: June 18, 2008Date of Patent: March 3, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Masayuki Soutome, Eiji Mochizuki, Syuuji Miyashita, Masahiro Kikuchi