Patents by Inventor Masayuki Sugasawa

Masayuki Sugasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5184212
    Abstract: A circuit for producing a brightness signal from output color signals of a solid state image pick-up apparatus. The circuit comprises a delay circuit for delaying an output signal generated by one solid state image sensor by a delay time corresponding to one-half of a spatial sampling period so that the phase of the output signal of the one solid state image sensor is made to coincide with the phase of an output signal of another solid state image sensor. A first filter is provided for cutting off higher frequency components contained in the output signal of the delay circuit and in the output signal of the other solid state image sensor, and a signal processor is provided for processing output signals of the first filter.
    Type: Grant
    Filed: September 6, 1991
    Date of Patent: February 2, 1993
    Assignee: Ikegami Tsushinki Co., Ltd.
    Inventors: Kazumi Yamamoto, Masayuki Sugasawa
  • Patent number: 5124785
    Abstract: A color television image processing apparatus having a color fading reduction function which compresses the luminance signal and color difference signals with different compression ratios. Color fading can be prevented even for high luminance images colored by complicated mixtures of red, green and blue signals.
    Type: Grant
    Filed: October 1, 1990
    Date of Patent: June 23, 1992
    Assignee: Ikegami Tsushinki Co., Ltd.
    Inventors: Iwao Hirose, Kazumi Yamamoto, Masayuki Sugasawa
  • Patent number: 5019895
    Abstract: Common use of 1H delay circuits (14 and 15), which are used as parts of a contour correction circuit (17) and a comb filter for reducing the interference between the luminance signal and the color signal (cross color noises), reduces the required number of the 1H delay circuits, and the space for mounting the 1H delay circuits, and reduces the cost.
    Type: Grant
    Filed: June 5, 1990
    Date of Patent: May 28, 1991
    Assignee: Ikegami Tsushinki Co., Ltd.
    Inventors: Kazumi Yamamoto, Masayuki Sugasawa