Abstract: The semiconductor device includes a transmitting-side hierarchical block, a receiving-side hierarchical block and an inter-block circuit. The transmitting-side hierarchical block includes a first logic circuit and an output control circuit connected to the first logic circuit and controlling an output signal of the transmitting-side hierarchical block. The receiving-side hierarchical block includes a second logic circuit being scan test target and operating by receiving the output signal of the transmitting-side hierarchical block, and a test control circuit controlling the scan test of the second logic circuit. The inter-block circuit transmits the output signal of the transmitting-side hierarchical block to the receiving-side hierarchical block.

Abstract: The semiconductor device includes a transmitting-side hierarchical block, a receiving-side hierarchical block and an inter-block circuit. The transmitting-side hierarchical block includes a first logic circuit and an output control circuit connected to the first logic circuit and controlling an output signal of the transmitting-side hierarchical block. The receiving-side hierarchical block includes a second logic circuit being scan test target and operating by receiving the output signal of the transmitting-side hierarchical block, and a test control circuit controlling the scan test of the second logic circuit. The inter-block circuit transmits the output signal of the transmitting-side hierarchical block to the receiving-side hierarchical block.

Abstract: A semiconductor device includes a semiconductor chip, which includes a substrate, a multilayer interconnect layer formed over the substrate, a first cell column disposed along an edge of the substrate in a plan view, the first cell column having a first I/O cell and a first power supply cell, second cell column disposed along the first cell column in plan view, the second cell column having a second I/O cell, a first pad supplying a first supply voltage to the first power supply cell, a first voltage supply wire disposed over the first cell column, a second voltage supply wire disposed over the second cell column, and a first connection wire crossing the first voltage supply wire and the second voltage supply wire.

Abstract: A semiconductor device includes a multilayer interconnect layer formed over a substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column including a first I/O cell, first and second inner peripheral cell columns formed at an inner peripheral side of the outer peripheral cell column, the first and second inner peripheral cell columns including a second I/O cell, and signal interconnects for forming an internal circuit of the semiconductor device, arranged between the first inner peripheral cell column and the second inner peripheral cell column.

Abstract: A semiconductor device includes a semiconductor chip, the semiconductor chip including a substrate, a multilayer interconnect layer formed over the substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column having at least one first I/O cell, and an inner peripheral cell column formed at an inner peripheral side of the outer peripheral cell column, the inner peripheral cell column having at least one second I/O cell.

Abstract: A semiconductor device includes a semiconductor chip, the semiconductor chip including a substrate, a multilayer interconnect layer formed over the substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column having at least one first I/O cell, and an inner peripheral cell column formed at an inner peripheral side of the outer peripheral cell column, the inner peripheral cell column having at least one second I/O cell.

Abstract: A potential-supply connection interconnect is provided in a multilayer interconnect layer. The potential supply connection interconnect overlaps some cell of I/O cells in the outer peripheral cell column and some cell of I/O cells in the inner peripheral cell column in a plan view. The potential-supply connection interconnect connects a power potential supply interconnect located below the outer peripheral cell column to a power potential supply interconnect located below the inner peripheral cell column and also connects a ground potential supply interconnect located below the outer peripheral cell column to a ground potential supply interconnect located below the inner peripheral cell column.

Abstract: A potential-supply connection interconnect is provided in a multilayer interconnect layer. The potential supply connection interconnect overlaps some cell of I/O cells in the outer peripheral cell column and some cell of I/O cells in the inner peripheral cell column in a plan view. The potential-supply connection interconnect connects a power potential supply interconnect located below the outer peripheral cell column to a power potential supply interconnect located below the inner peripheral cell column and also connects a ground potential supply interconnect located below the outer peripheral cell column to a ground potential supply interconnect located below the inner peripheral cell column.

Abstract: A resistance wiring and a judgement circuit for judging a potential in a middle of a path of the resistance wiring are provided on a periphery of a semiconductor chip. One end of the resistance wiring is connected to a power supply and the other end thereof is grounded. Connection points of the resistance wiring to the power supply and the ground are disposed at a corner on the periphery of the semiconductor chip, while a connection point of the resistance wiring to the judgement circuit is disposed at a corner diagonal to the corner on the periphery. When breakages such as chipping and peeling of an interlayer insulating film is caused on the periphery, resistance of the resistance wiring changes.

Abstract: A resistance wiring (12) and a judgement circuit (14) for judging a potential in a middle of a path of the resistance wiring (12) are provided on a periphery of a semiconductor chip (11). One end of the resistance wiring (12) is connected to a power supply (Vcc) and the other end thereof is grounded. Connection points of the resistance wiring (12) to the power supply (Vcc) and the ground are disposed at a corner (P1) on the periphery of the semiconductor chip, while a connection point of the resistance wiring (12) to the judgement circuit (14) is disposed at a corner (P2) diagonal to the corner (P1) on the periphery. According to a semiconductor device structured in this way, when breakages such as chipping (B) and peeling of an interlayer insulating film is caused on the periphery, resistance of the resistance wiring (12) changes.