Patents by Inventor Masayuki Yanagisawa
Masayuki Yanagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9217770Abstract: A probe resistance measuring method includes measuring first resistances at three or more nodes by making contact at least a part of a plurality of probes of a probe unit with three or more pads for resistance measurement based on a first correspondence relation. The measured resistances are stored as a first measurement result and contact resistances of the plurality of probes of the probe unit are calculated based on the first measurement result.Type: GrantFiled: August 31, 2012Date of Patent: December 22, 2015Assignee: Renesas Electronics CorporationInventors: Shigetomi Michimata, Masayuki Yanagisawa, Kazumasa Kuroyanagi
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Publication number: 20130001551Abstract: A probe resistance measuring method includes measuring first resistances at three or more nodes by making contact at least a part of a plurality of probes of a probe unit with three or more pads for resistance measurement based on a first correspondence relation. The measured resistances are stored as a first measurement result and contact resistances of the plurality of probes of the probe unit are calculated based on the first measurement result.Type: ApplicationFiled: August 31, 2012Publication date: January 3, 2013Inventors: Shigetomi MICHIMATA, Masayuki YANAGISAWA, Kazumasa KUROYANAGI
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Patent number: 8278935Abstract: A probe resistance measuring method includes measuring first resistances at three or more nodes by making contact at least a part of a plurality of probes of a probe unit with three or more pads for resistance measurement based on a first correspondence relation. The measured resistances are stored as a first measurement result and contact resistances of the plurality of probes of the probe unit are calculated based on the first measurement result.Type: GrantFiled: April 4, 2008Date of Patent: October 2, 2012Assignee: Renesas Electronics CorporationInventors: Shigetomi Michimata, Masayuki Yanagisawa, Kazumasa Kuroyanagi
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Publication number: 20110079834Abstract: A semiconductor integrated circuit device has: a MISFET having source/drain diffusion layers; first plugs respectively connected to the source/drain diffusion layers; a first interconnection connected to one of the source/drain diffusion layers through the first plug; a second plug electrically connected to the other Of the source/drain diffusion layers through the first plug; a second interconnection connected to the second plug; and a capacitor electrode located above a gate electrode of the MISFET. The first interconnection is formed not above the lower capacitor electrode, while the second interconnection is formed above the upper capacitor electrode. A plug connecting the first interconnection and another interconnection is not provided at an upper location of the one of the source/drain diffusion layers. The first interconnection is not provided at an upper location of the other of the source/drain diffusion layers.Type: ApplicationFiled: October 1, 2010Publication date: April 7, 2011Applicant: Renesas Electronics CorporationInventors: Masayuki YANAGISAWA, Hiroshi Furuta, Hiroyasu Kitajima, Katsuya Izumi
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Patent number: 7879532Abstract: A method of manufacturing a semiconductor device includes: (A) providing a wafer to which a photo-resist is applied; (B) forming a reacted portion in the photo-resist by exposing the wafer to a light through a mask having a translucent section, the reacted portion being a portion reacted with the light; and (C) forming a resist mask having an opening portion corresponding to the translucent section by dissolving the reacted portion. The opening portion does not penetrate the photo-resist in a case where an exposure amount in the (B) process is a first exposure amount. On the other hand, the opening portion penetrates the photo-resist in a case where the exposure amount is a second exposure amount larger than the first exposure amount.Type: GrantFiled: June 29, 2006Date of Patent: February 1, 2011Assignee: Renesas Electronics CorporationInventor: Masayuki Yanagisawa
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Publication number: 20090008641Abstract: A probe resistance measuring method includes measuring first resistances at three or more nodes by making contact at least a part of a plurality of probes of a probe unit with three or more pads for resistance measurement based on a first correspondence relation. The measured resistances are stored as a first measurement result and contact resistances of the plurality of probes of the probe unit are calculated based on the first measurement result.Type: ApplicationFiled: April 4, 2008Publication date: January 8, 2009Inventors: Shigetomi Michimata, Masayuki Yanagisawa, Kazumasa Kuroyanagi
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Patent number: 7361967Abstract: A semiconductor device wherein return wires corresponding to a plurality of fuse wires are arranged collectively in the same region. Moreover, the return wires are arranged in multiple layers. This arrangement creates a region where no return wire is disposed between the fuse wires, thereby permitting an arrangement of the fuse wires at the minimum wiring pitch. Alternatively, the semiconductor device may include fuse strings arranged in a plurality of stages and a plurality of connection wires for supplying signals to the fuse strings in the plurality of stages, respectively, wherein connection wires for other fuse strings are arranged in a region between adjacent fuse strings.Type: GrantFiled: February 7, 2005Date of Patent: April 22, 2008Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Masayuki Yanagisawa, Masatoshi Sonoda, Yoshinori Ueno
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Publication number: 20070009836Abstract: A method of manufacturing a semiconductor device includes: (A) providing a wafer to which a photo-resist is applied; (B) forming a reacted portion in the photo-resist by exposing the wafer to a light through a mask having a translucent section, the reacted portion being a portion reacted with the light; and (C) forming a resist mask having an opening portion corresponding to the translucent section by dissolving the reacted portion. The opening portion does not penetrate the photo-resist in a case where an exposure amount in the (B) process is a first exposure amount. On the other hand, the opening portion penetrates the photo-resist in a case where the exposure amount is a second exposure amount larger than the first exposure amount.Type: ApplicationFiled: June 29, 2006Publication date: January 11, 2007Inventor: Masayuki Yanagisawa
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Publication number: 20050181680Abstract: A semiconductor device wherein return wires corresponding to a plurality of fuse wires are arranged collectively in the same region. Moreover, the return wires are arranged in multiple layers. This arrangement creates a region where no return wire is disposed between the fuse wires, thereby permitting an arrangement of the fuse wires at the minimum wiring pitch. Alternatively, the semiconductor device may include fuse strings arranged in a plurality of stages and a plurality of connection wires for supplying signals to the fuse strings in the plurality of stages, respectively, wherein connection wires for other fuse strings are arranged in a region between adjacent fuse strings.Type: ApplicationFiled: February 7, 2005Publication date: August 18, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Hiroyuki Takahashi, Masayuki Yanagisawa, Masatoshi Sonoda, Yoshinori Ueno
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Patent number: 5290711Abstract: In a method for fabricating a semiconductor device of the present invention, photoresist layers are not formed on a scribe line regions entirely. Therefore, electric charge can be transferred from device regions to out of a wafer by surface conduction, when impurity layers are formed on a substrate by ion implantation.Type: GrantFiled: April 28, 1993Date of Patent: March 1, 1994Assignee: NEC CorporationInventor: Masayuki Yanagisawa
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Patent number: 5262258Abstract: A process of manufacturing semiconductor devices includes a step of transferring on a surface of a semiconductor wafer by a step-and-repeat reduction projection system a pair of rotation error check patterns formed as a main scale and a vernier scale. In one form, the transfer also includes a pair of resolution check patterns disposed respectively adjacent to the main scale and the vernier scale. In another form, the process includes a first step of transferring a mask pattern including a main or a vernier alignment scale having an alignment check patterns and a second step of transferring, after the completion of said first step, another mask pattern including another main or vernier alignment scale having an alignment check patterns and this second step includes transferring of rotation error check patterns and resolution check patterns.Type: GrantFiled: June 12, 1991Date of Patent: November 16, 1993Assignee: NEC CorporationInventor: Masayuki Yanagisawa
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Patent number: 5187550Abstract: A storage electrode of a trench capacitor is connected through a trench side wall contact hole to a source/drain region. A p.sup.+ region is provided between the source/drain region and an n.sup.+ region which is a part of a cell plate, and is opposite through a silicon oxide film and a capacitive insulation film to the storage electrode.Type: GrantFiled: January 27, 1992Date of Patent: February 16, 1993Assignee: NEC CorporationInventor: Masayuki Yanagisawa
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Patent number: 4806457Abstract: A method of manufacturing integrated circuit semiconductor device in which a check pattern of resist film is formed for monitoring a state of an element-forming resist pattern having a narrow interval of 1.0 .mu.m or less is disclosed. The check pattern is designed such that a plurality of resist stripes are arranged with intervals therebetween. Each of the intervals is of 1.0 .mu.m or less and the width of the resist stripe is three times or more the interval.Type: GrantFiled: April 9, 1987Date of Patent: February 21, 1989Assignee: NEC CorporationInventor: Masayuki Yanagisawa