Abstract: A high frequency variable attenuation circuit includes an input terminal, an output terminal, a first resistor, a second resistor, a third resistor, and a first switching circuit. The first switching circuit has an output side resistor and an output side switching element that are connected in series to each other. The first switching circuit has a first circuit end connected to the second end of the second resistor and the output terminal, and a second circuit end connected to the ground.

Abstract: A first phase setting circuit generates a first phase setting signal. A first synchronous signal generator generates a first synchronous clock signal having a phase set by the first phase setting signal from a multi-phase local clock signal. By removing a phase fluctuation component representing phase fluctuation of the reception data signal from a first signal including a frequency component representing a frequency offset between a multi-phase local clock signal and a reception data signal and the phase fluctuation component, a second generation unit generates a second signal including the frequency component. The first phase setting circuit updates the first phase setting signal according to the second signal.

Abstract: Exemplary receiving apparatus receives serial data that includes contiguous blocks each having M-bit known pattern. The apparatus includes a serial-parallel conversion circuit that arranges bits in the serial data to generates N-bit wide (N<M) parallel data, a register group including a first register that stores a word of the parallel data and second registers to which the word of the parallel data is sequentially shifted and stored, a comparing circuit that compares the known pattern with storage patterns each including M contiguous bits stored in the register group, and a detecting circuit. The detecting circuit detects reception of the serial data if the comparing circuit detects a first match between the known pattern and a first one of the storage patterns, and a second match between the known pattern and a second one of the storage patterns that starts with a specific bit during a specific clock cycle.

Abstract: A first phase setting circuit generates a first phase setting signal. A first synchronous signal generator generates a first synchronous clock signal having a phase set by the first phase setting signal from a multi-phase local clock signal. By removing a phase fluctuation component representing phase fluctuation of the reception data signal from a first signal including a frequency component representing a frequency offset between a multi-phase local clock signal and a reception data signal and the phase fluctuation component, a second generation unit generates a second signal including the frequency component. The first phase setting circuit updates the first phase setting signal according to the second signal.

Abstract: Exemplary receiving apparatus receives serial data that includes contiguous blocks each having M-bit known pattern. The apparatus includes a serial-parallel conversion circuit that arranges bits in the serial data to generates N-bit wide (N<M) parallel data, a register group including a first register that stores a word of the parallel data and second registers to which the word of the parallel data is sequentially shifted and stored, a comparing circuit that compares the known pattern with storage patterns each including M contiguous bits stored in the register group, and a detecting circuit. The detecting circuit detects reception of the serial data if the comparing circuit detects a first match between the known pattern and a first one of the storage patterns, and a second match between the known pattern and a second one of the storage patterns that starts with a specific bit during a specific clock cycle.

Abstract: In one of a digital circuit and a semiconductor device, each having a scan chain, a clock fed to a clock input terminal of a flipflop forming the scan chain is switched between during a shift mode and during a capture mode. The time interval from the last clock pulse of the clock signal selected during the shift mode to the first clock pulse of the clock signal selected during the capture mode is set to be shorter than the pulse interval (period) between adjacent pulses of the clock signal selected during the shift mode. In this arrangement, a low-speed tester operates at a substantially high speed, permitting scan-path testing to be carried out with low cost involved.

Abstract: In one of a digital circuit and a semiconductor device, each having a scan chain, a clock fed to a clock input terminal of a flipflop forming the scan chain is switched between during a shift mode and during a capture mode. The time interval from the last clock pulse of the clock signal selected during the shift mode to the first clock pulse of the clock signal selected during the capture mode is set to be shorter than the pulse interval (period) between adjacent pulses of the clock signal selected during the shift mode. In this arrangement, a low-speed tester operates at a substantially high speed, permitting scan-path testing to be carried out with low cost involved.

Abstract: A semiconductor integrated circuit and method of use improve a rate of defect detection and also facilitate production of test patterns while suppressing an increase of the circuit area. The semiconductor integrated circuit includes a plurality of pairs of a sequence circuit and selector circuit. Each of the sequence circuits stores an operation result of an internal circuit, whereas each selector circuit is responsive to a control signal for selecting one of the data stored in its associated sequence circuit and an inverted version of the data to thereby output the selected data. A control circuit operates to count up or divide clocks and then control the selector circuits constituting the plurality of pairs in accordance with the resultant count values.