Patents by Inventor Masazi Mito

Masazi Mito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of integrating MOS devices of double and single gate structure
    Patent number: 4495693
    Abstract: A nonvolatile semiconductor memory device is provided having a MOS transistor and a floating gate type MOS transistor. The length of an overlap between a floating gate and a drain region of the floating gate type MOS transistor is made smaller than that of an overlap between the gate and the drain region of the MOS transistor.
    Type: Grant
    Filed: April 22, 1983
    Date of Patent: January 29, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hiroshi Iwahashi, Masamichi Asano, Kuniyoshi Yoskikawa, Masazi Mito
  • Semiconductor integrated circuit device with non-volatile semiconductor memory cells and means for relieving stress therein
    Patent number: 4453174
    Abstract: Disclosed is a metal oxide semiconductor integrated circuit device having an array of electrically rewritable, insulated gate type non-volatile semiconductor memory cells formed on a semiconductor substrate, read/write mode setting circuit and address designating circuits arranged corresponding to the memory cell array, those circuits being fabricated on the substrate, and a field insulating layer formed on the substrate. A cut portion is formed in the field insulating layer to surround the memory cell array.
    Type: Grant
    Filed: May 22, 1980
    Date of Patent: June 5, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yuichi Kawasaki, Sumio Tanaka, Hiroshi Iwahashi, Masamichi Asano, Shinichi Maekawa, Masazi Mito