Patents by Inventor Masazumi Maeda
Masazumi Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210034541Abstract: A memory system includes a memory that includes a buffer region having a plurality of buffer storage regions, each buffer storage region including a plurality of buffer memory cells, the plurality of buffer memory cells being cells storing data of 1 bit or a plurality of bits in units of the buffer storage regions, and a first storage region having a plurality of first storage regions including the plurality of first memory cells storing data of a plurality of bits; and a control circuit that changes at least one buffer storage region in which data is written to at least one first storage region, and changes at least one free first storage region into at least one buffer storage region to replace the changed at least one buffer storage region.Type: ApplicationFiled: July 29, 2020Publication date: February 4, 2021Applicant: FUJITSU LIMITEDInventor: Masazumi MAEDA
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Patent number: 10720202Abstract: An apparatus for memory control includes a data storage area configured to store data indicative of a distribution of total current consumption required for a write operation as measured with respect to one or more nonvolatile memory devices of a first type, and a control apparatus configured to evaluate, based on the data indicative of the distribution, a degree to which a total amount of current consumption required for a write operation with respect to a memory area in a nonvolatile memory device of the same first type, regarding a current flowing from a power supply to the nonvolatile memory device during the write operation, is deviated toward larger total current consumptions in the distribution, thereby determining whether the memory area is satisfactory.Type: GrantFiled: August 9, 2019Date of Patent: July 21, 2020Assignee: FUJITSU LIMITEDInventors: Masazumi Maeda, Kazuko Higurashi
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Memory controller, information processing system, and nonvolatile-memory defect determination method
Patent number: 10614901Abstract: A memory controller includes a memory that stores therein data corresponding to a distribution of write durations measured from a nonvolatile memory device of a specific model, and a processor that measures a write duration taken to write data to a memory cell in a nonvolatile memory device of a same model as the specific model and that determines whether or not the memory cell is defective by evaluating, based on the data corresponding to the distribution, a displacement of the measured write duration from a center portion of the distribution.Type: GrantFiled: August 1, 2018Date of Patent: April 7, 2020Assignee: FUJITSU LIMITEDInventor: Masazumi Maeda -
Publication number: 20200066322Abstract: An apparatus for memory control includes a data storage area configured to store data indicative of a distribution of total current consumption required for a write operation as measured with respect to one or more nonvolatile memory devices of a first type, and a control apparatus configured to evaluate, based on the data indicative of the distribution, a degree to which a total amount of current consumption required for a write operation with respect to a memory area in a nonvolatile memory device of the same first type, regarding a current flowing from a power supply to the nonvolatile memory device during the write operation, is deviated toward larger total current consumptions in the distribution, thereby determining whether the memory area is satisfactory.Type: ApplicationFiled: August 9, 2019Publication date: February 27, 2020Applicant: FUJITSU LIMITEDInventors: Masazumi MAEDA, Kazuko HIGURASHI
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Patent number: 10497445Abstract: A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.Type: GrantFiled: July 17, 2018Date of Patent: December 3, 2019Assignee: FUJITSU LIMITEDInventors: Masahiro Ise, Masazumi Maeda
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Patent number: 10409686Abstract: An apparatus includes first and second circuits that transmit and receive information to and from each other through first paths, where each of the first and second circuits includes second paths respectively coupled to the first paths, and matrix switches that are provided across the second paths and switch a transmission path of information transmitted to any one of the second paths. Upon detecting an error in the second paths, the apparatus conducts a loop-back test in which each matrix switch is switched to a loop-back state in which information to be transmitted to the second path in which the error has been detected, is looped back. Upon detecting an error in the loop-back test, the apparatus switches the matrix switches to a bypass state in which the second path in which the error is detected is bypassed to another one of the second paths to continue the loop-back test.Type: GrantFiled: October 25, 2017Date of Patent: September 10, 2019Assignee: FUJITSU LIMITEDInventors: Masazumi Maeda, Koji Migita
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Patent number: 10256798Abstract: A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal; and a logic circuit processes the input signal to the delay line and the delayed signal.Type: GrantFiled: November 7, 2016Date of Patent: April 9, 2019Assignee: FUJITSU LIMITEDInventors: Noriyuki Tokuhiro, Masazumi Maeda
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Patent number: 10249371Abstract: A control circuit that controls a memory including a storage region and a redundant region, the control circuit includes a detector that detects a defective block in the memory, and a controller that switches, when the detector has detected the defective block, a data storage scheme of the first block detected as the defective block from a first storage scheme to a second storage scheme in which the number of bits of data to be stored in each of memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the first storage scheme, and that stores a portion of data stored in the first block in the first storage scheme to be stored in the first block in the second storage scheme.Type: GrantFiled: September 28, 2017Date of Patent: April 2, 2019Assignee: FUJITSU LIMITEDInventor: Masazumi Maeda
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MEMORY CONTROLLER, INFORMATION PROCESSING SYSTEM, AND NONVOLATILE-MEMORY DEFECT DETERMINATION METHOD
Publication number: 20190057753Abstract: A memory controller includes a memory that stores therein data corresponding to a distribution of write durations measured from a nonvolatile memory device of a specific model, and a processor that measures a write duration taken to write data to a memory cell in a nonvolatile memory device of a same model as the specific model and that determines whether or not the memory cell is defective by evaluating, based on the data corresponding to the distribution, a displacement of the measured write duration from a center portion of the distribution.Type: ApplicationFiled: August 1, 2018Publication date: February 21, 2019Applicant: FUJITSU LIMITEDInventor: Masazumi MAEDA -
Publication number: 20190035469Abstract: A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.Type: ApplicationFiled: July 17, 2018Publication date: January 31, 2019Applicant: FUJITSU LIMITEDInventors: Masahiro Ise, Masazumi MAEDA
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Patent number: 10002670Abstract: A memory includes a memory cell including a memory transistor in which electric charges are stored in an electric charge storage layer when data is written to the memory cell, and a controller configured to control a voltage to be applied to the memory transistor in a predetermined hold time until an amount of electric charges stored in the electric charge storage layer decreases to an amount of electric charges corresponding to a state where the data is erased from the memory cell.Type: GrantFiled: March 22, 2017Date of Patent: June 19, 2018Assignee: FUJITSU LIMITEDInventors: Masazumi Maeda, Masahiro Ise
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Publication number: 20180137008Abstract: An apparatus includes first and second circuits that transmit and receive information to and from each other through first paths, where each of the first and second circuits includes second paths respectively coupled to the first paths, and matrix switches that are provided across the second paths and switch a transmission path of information transmitted to any one of the second paths. Upon detecting an error in the second paths, the apparatus conducts a loop-back test in which each matrix switch is switched to a loop-back state in which information to be transmitted to the second path in which the error has been detected, is looped back. Upon detecting an error in the loop-back test, the apparatus switches the matrix switches to a bypass state in which the second path in which the error is detected is bypassed to another one of the second paths to continue the loop-back test.Type: ApplicationFiled: October 25, 2017Publication date: May 17, 2018Applicant: FUJITSU LIMITEDInventors: Masazumi Maeda, Koji Migita
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Publication number: 20180122480Abstract: A control circuit that controls a memory including a storage region and a redundant region, the control circuit includes a detector that detects a defective block in the memory, and a controller that switches, when the detector has detected the defective block, a data storage scheme of the first block detected as the defective block from a first storage scheme to a second storage scheme in which the number of bits of data to be stored in each of memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the first storage scheme, and that stores a portion of data stored in the first block in the first storage scheme to be stored in the first block in the second storage scheme.Type: ApplicationFiled: September 28, 2017Publication date: May 3, 2018Applicant: FUJITSU LIMITEDInventor: Masazumi MAEDA
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Publication number: 20170301401Abstract: A memory includes a memory cell including a memory transistor in which electric charges are stored in an electric charge storage layer when data is written to the memory cell, and a controller configured to control a voltage to be applied to the memory transistor in a predetermined hold time until an amount of electric charges stored in the electric charge storage layer decreases to an amount of electric charges corresponding to a state where the data is erased from the memory cell.Type: ApplicationFiled: March 22, 2017Publication date: October 19, 2017Applicant: FUJITSU LIMITEDInventors: Masazumi MAEDA, Masahiro Ise
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Patent number: 9742413Abstract: An electronic device includes: a voltage controlled delay line including delay elements configured to delay an input clock signal and output the clock signal, a delay control element configured to control a delay time of the clock signal delayed by the delay elements in accordance with a control voltage, a delay sensitivity adjustment circuit configured to adjust a ratio of an amount of change of the delay time to an amount of change of the control voltage, and a plurality of delay circuits; and a control voltage generation circuit configured to compare a phase of an output signal of any one of the plurality of delay circuits and a phase of the clock signal, generate the control voltage so as to match the phase of the output signal and the phase of the clock signal based on the comparison result, and output the control voltage to the delay control element.Type: GrantFiled: June 18, 2015Date of Patent: August 22, 2017Assignee: FUJITSU LIMITEDInventors: Yoshiharu Yoshizawa, Masazumi Maeda
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Publication number: 20170163250Abstract: A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal; and a logic circuit that performs logical calculation of the input signal to the delay line and the delayed signal.Type: ApplicationFiled: November 7, 2016Publication date: June 8, 2017Applicant: FUJITSU LIMITEDInventors: Noriyuki Tokuhiro, Masazumi MAEDA
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Publication number: 20170163268Abstract: A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and outputs the input signal as a delayed signal; and a delay line control circuit that generates the delay setting signal in accordance with delay setting data used to specify a delay value in stages and outputs the delay setting signal to the delay line, the delay line control circuit including a conversion circuit that replaces delay setting data to be modified in which a delay amount of a certain range is not obtained with respect to a change in a value of the delay setting data with normal delay setting data in which a delay amount of a certain change range is obtained and that is adjacent to the delay setting data to be modified, and outputs the delay setting data to the delay line.Type: ApplicationFiled: October 25, 2016Publication date: June 8, 2017Applicant: FUJITSU LIMITEDInventors: Masazumi MAEDA, Noriyuki Tokuhiro
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Patent number: 9571110Abstract: A delay circuit comprises a plurality of delay buffers each including two or more serially connected delay units, each of the delay units being capable of variably controlling a delay amount; a variable control voltage generator circuit configured to supply, to a first delay unit included in each of the plurality of delay buffers, a variable control voltage provided to control the delay amount of the first delay unit; and a fixed control voltage generator circuit configured to supply, to a second delay unit included in each of the plurality of delay buffers, a fixed control voltage among a plurality of fixed control voltages for controlling the delay amount of the second delay unit. The plurality of delay buffers are connected in series and an input signal propagates through the plurality of serially connected delay buffers.Type: GrantFiled: August 26, 2015Date of Patent: February 14, 2017Assignee: FUJITSU LIMITEDInventors: Masazumi Maeda, Yoshiharu Yoshizawa
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Patent number: 9362877Abstract: An electronic component includes: a first amplifier configured to amplify one of differential signals; a second amplifier configured to amplify another one of the differential signals; a sensor configured to measure voltages of a first output signal outputted from the first amplifier and a second output signal outputted from the second amplifier; and a controller configured to control, based on the voltages measured by the sensor, either one or both of a current and a resistance value of the first amplifier so that a common voltage of the first output signal and a common voltage of the second output signal are approximate to each other.Type: GrantFiled: May 12, 2014Date of Patent: June 7, 2016Assignee: FUJITSU LIMITEDInventors: Masazumi Maeda, Yoshiharu Yoshizawa
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Publication number: 20160105189Abstract: A delay circuit comprises a plurality of delay buffers each including two or more serially connected delay units, each of the delay units being capable of variably controlling a delay amount; a variable control voltage generator circuit configured to supply, to a first delay unit included in each of the plurality of delay buffers, a variable control voltage provided to control the delay amount of the first delay unit; and a fixed control voltage generator circuit configured to supply, to a second delay unit included in each of the plurality of delay buffers, a fixed control voltage among a plurality of fixed control voltages for controlling the delay amount of the second delay unit. The plurality of delay buffers are connected in series and an input signal propagates through the plurality of serially connected delay buffers.Type: ApplicationFiled: August 26, 2015Publication date: April 14, 2016Inventors: Masazumi MAEDA, Yoshiharu YOSHIZAWA