Patents by Inventor Masazumi Matsuura

Masazumi Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9991162
    Abstract: A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 5, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Masazumi Matsuura
  • Publication number: 20170294352
    Abstract: A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Applicant: Renesas Electronics Corporation
    Inventor: Masazumi MATSUURA
  • Patent number: 9721873
    Abstract: A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 1, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Masazumi Matsuura
  • Patent number: 9368459
    Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 14, 2016
    Assignee: ACACIA RESEARCH GROUP LLC
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Patent number: 9245800
    Abstract: To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: January 26, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masazumi Matsuura
  • Publication number: 20150311116
    Abstract: To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.
    Type: Application
    Filed: April 30, 2015
    Publication date: October 29, 2015
    Inventor: Masazumi MATSUURA
  • Patent number: 9035460
    Abstract: To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masazumi Matsuura
  • Publication number: 20150108613
    Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 23, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Takeshi FURUSAWA, Noriko MIURA, Kinya GOTO, Masazumi MATSUURA
  • Patent number: 8963291
    Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Publication number: 20140138848
    Abstract: A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 22, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Masazumi MATSUURA
  • Patent number: 8018030
    Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: September 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Publication number: 20110215447
    Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Application
    Filed: May 20, 2011
    Publication date: September 8, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Takeshi Furusawa, Norio Miura, Kinya Goto, Masazumi Matsuura
  • Patent number: 7981790
    Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
  • Patent number: 7960279
    Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: June 14, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Publication number: 20100112805
    Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.
    Type: Application
    Filed: January 7, 2010
    Publication date: May 6, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
  • Patent number: 7671473
    Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: March 2, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
  • Publication number: 20090263963
    Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 22, 2009
    Applicant: Renesas Technology Corp.
    Inventors: Takeshi FURUSAWA, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Patent number: 7605448
    Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: October 20, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Patent number: 7602063
    Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: October 13, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Publication number: 20090189245
    Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Application
    Filed: March 24, 2009
    Publication date: July 30, 2009
    Applicant: Renesas Technology Corporation
    Inventors: Takeshi FURUSAWA, Noriko Miura, Kinya Goto, Masazumi Matsuura