Patents by Inventor Masazumi Matsuura
Masazumi Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9991162Abstract: A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.Type: GrantFiled: June 26, 2017Date of Patent: June 5, 2018Assignee: Renesas Electronics CorporationInventor: Masazumi Matsuura
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Publication number: 20170294352Abstract: A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Applicant: Renesas Electronics CorporationInventor: Masazumi MATSUURA
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Patent number: 9721873Abstract: A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.Type: GrantFiled: November 19, 2013Date of Patent: August 1, 2017Assignee: Renesas Electronics CorporationInventor: Masazumi Matsuura
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Patent number: 9368459Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: GrantFiled: December 23, 2014Date of Patent: June 14, 2016Assignee: ACACIA RESEARCH GROUP LLCInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Patent number: 9245800Abstract: To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.Type: GrantFiled: April 30, 2015Date of Patent: January 26, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Masazumi Matsuura
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Publication number: 20150311116Abstract: To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.Type: ApplicationFiled: April 30, 2015Publication date: October 29, 2015Inventor: Masazumi MATSUURA
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Patent number: 9035460Abstract: To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.Type: GrantFiled: November 15, 2012Date of Patent: May 19, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Masazumi Matsuura
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Publication number: 20150108613Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: ApplicationFiled: December 23, 2014Publication date: April 23, 2015Applicant: Renesas Electronics CorporationInventors: Takeshi FURUSAWA, Noriko MIURA, Kinya GOTO, Masazumi MATSUURA
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Patent number: 8963291Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: GrantFiled: May 20, 2011Date of Patent: February 24, 2015Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20140138848Abstract: A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.Type: ApplicationFiled: November 19, 2013Publication date: May 22, 2014Applicant: Renesas Electronics CorporationInventor: Masazumi MATSUURA
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Patent number: 8018030Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: GrantFiled: March 24, 2009Date of Patent: September 13, 2011Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20110215447Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: ApplicationFiled: May 20, 2011Publication date: September 8, 2011Applicant: Renesas Electronics CorporationInventors: Takeshi Furusawa, Norio Miura, Kinya Goto, Masazumi Matsuura
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Patent number: 7981790Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.Type: GrantFiled: January 7, 2010Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
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Patent number: 7960279Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.Type: GrantFiled: June 29, 2009Date of Patent: June 14, 2011Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20100112805Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.Type: ApplicationFiled: January 7, 2010Publication date: May 6, 2010Applicant: Renesas Technology Corp.Inventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
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Patent number: 7671473Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.Type: GrantFiled: June 14, 2006Date of Patent: March 2, 2010Assignee: Renesas Technology Corp.Inventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
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Publication number: 20090263963Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.Type: ApplicationFiled: June 29, 2009Publication date: October 22, 2009Applicant: Renesas Technology Corp.Inventors: Takeshi FURUSAWA, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Patent number: 7605448Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: GrantFiled: September 8, 2005Date of Patent: October 20, 2009Assignee: Renesas Technology Corp.Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Patent number: 7602063Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.Type: GrantFiled: July 5, 2005Date of Patent: October 13, 2009Assignee: Renesas Technology Corp.Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20090189245Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: ApplicationFiled: March 24, 2009Publication date: July 30, 2009Applicant: Renesas Technology CorporationInventors: Takeshi FURUSAWA, Noriko Miura, Kinya Goto, Masazumi Matsuura