Patents by Inventor Mashuhiro Yamada

Mashuhiro Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Variable delay circuit
    Patent number: 5440260
    Abstract: The gate of a CMOS transistor formed by a series connection of p-channel and n-channel FETs 21 and 22 is connected to an input terminal 23, and the drain of the CMOS transistor is connected to an output terminal 24. The source of the FET 21 is connected to a positive power supply terminal 20 via parallel-connected switchable resistance elements 37.sub.0, 37.sub.1, 37.sub.2, . . formed by p-channel FETs and having resistance values R.sub.0, R.sub.1, R.sub.2, . . . , respectively. The source of the other FET 22 is connected to a negative power supply terminal 30 via parallel-connected switchable resistance elements 38.sub.0, 38.sub.1, 38.sub.2, . . . formed by n-channel FETs and having resistance values R.sub.0, R.sub.1, R.sub.2, . . . , respectively. Delay setting signals S.sub.0, S.sub.1, . . . are decoded by a decoder 39 and one of more of its output terminals Y.sub.0, Y.sub.1 , . . . go to the high level. The output terminals Y.sub.0, Y.sub.1, Y.sub.2, . . .
    Type: Grant
    Filed: June 2, 1994
    Date of Patent: August 8, 1995
    Assignee: Advantest Corporation
    Inventors: Yokichi Hayashi, Hiroshi Tsukahara, Katsumi Ochiai, Mashuhiro Yamada, Naoyoshi Watanabe