Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to data specified by a single instruction of a processing element specifying an access to data.

Abstract: Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface unit. The arbitration unit provides an interface to one or more I/O agents that issue atomic transactions to access and/or modify data stored in a shared memory space accessed via the memory interface unit. The host interface unit interfaces to a front-side bus (FSB) to which one or more processors may be coupled. In response to an atomic transaction issued by an I/O agent, the transaction is forked into two interdependent processes. Under one process, an inbound write transaction is injected into the host interface unit, which then drives the FSB to cause the processor(s) to perform a cache snoop. At the same time, an inbound read transaction is injected into the memory interface unit, which retrieves a copy of the data from the shared memory space.

Abstract: In general, in one aspect, the disclosure describes a method that includes providing a memory access instruction of a processing element's instruction set including multiple parameters.

Abstract: A method and apparatus for adding an additional agent to a set of symmetric agents in a bus-based system is disclosed. In one embodiment, the number of symmetric agents in the system is fixed. An additional agent may monitor the symmetric arbitration of the symmetric agents, and at a given stage of the symmetric arbitration assert a priority agent bus request. The priority agent bus request may be shared with another priority agent. This may permit the additional agent to access the bus in a fair manner that behaves as though it were an additional symmetric agent in the system.

Abstract: A method, apparatus, and system for implementing off-chip cache memory in dual-use static random access memory (SRAM) memory for network processors. An off-chip SRAM memory store is partitioned into a resizable cache region and general-purpose use region (i.e., conventional SRAM use). The cache region is used to store cached data corresponding to portions of data contained in a second off-chip memory store, such as a dynamic RAM (DRAM) memory store or an alternative type of memory store, such as a Rambus DRAM (RDRAM) memory store. An on-chip cache management controller is integrated on the network processor. Various cache management schemes are disclosed, including hardware-based cache tag arrays, memory-based cache tag arrays, content-addressable memory (CAM)-based cache management, and memory address-to-cache line lookup schemes. Under one scheme, multiple network processors are enabled to access shared SRAM and shared DRAM, wherein a portion of the shared SRAM is used as a cache for the shared DRAM.

Abstract: An example embodiment of a method and apparatus for dynamically changing computer system configuration to improve software application performance includes a system logic device that implements at least two different configurations. The system logic device may change configuration depending on what software application is running. The system logic device can change configurations while the computer system is running and may change configurations in order to optimize performance for whatever application is currently running.

Abstract: A method of sampling data includes gathering a first data sample during execution of a program, executing the program during a random inter-sample period and gathering a second data sample following the inter-sample period. The method may also include generating an inter-sample count and decrementing the inter-sample count to zero before gathering the second data sample.

Abstract: A method and system are disclosed for measuring simultaneously and at randomly distributed intervals throughputs sets on one or more busses under test and displaying the percent occurrences of those throughputs sets in a graph as a density function. A method and system are also disclosed for simultaneously measuring throughput sets on one or more busses under test given that user specified stimuli are input into those busses and displaying those throughput sets in a graph as concurrency plots.