Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: In some embodiments, the invention involves a network controller having a pattern matching unit to identify whether boot file requested from a network accessible storage device for booting are stored locally in non-volatile memory accessible to the network controller. When required boot files are stored locally, the locally stored files are sent to the processor to boot the operating system. In an embodiment, retrieved boot files are automatically cached by the network controller in the accessible non-volatile memory. In other embodiments, a service operates to ensure coherency between locally store boot files and the boot filed stored on the network accessible storage. In another embodiment, data other than boot files may be stored and retrieved from the non-volatile memory. Other embodiments are described and claimed.

Abstract: A shorter and a longer text string may be compared. Instead of simply comparing the characters only one character at a time, more than one character can be compared at a time. In addition, a null terminated string may be detected. The shorter strings may be handled differently than longer strings.

Abstract: In some embodiments, the invention involves a network controller having a pattern matching unit to identify whether boot file requested from a network accessible storage device for booting are stored locally in non-volatile memory accessible to the network controller. When required boot files are stored locally, the locally stored files are sent to the processor to boot the operating system. In an embodiment, retrieved boot files are automatically cached by the network controller in the accessible non-volatile memory. In other embodiments, a service operates to ensure coherency between locally store boot files and the boot filed stored on the network accessible storage. In another embodiment, data other than boot files may be stored and retrieved from the non-volatile memory. Other embodiments are described and claimed.

Abstract: Disclosed is a multi-cell battery pack system that includes a plurality of cylindrical cells; a cradle with an interior surface that defines a channel extending through the length of the cradle and an exterior surface that mechanically positions each of the cells radially around and parallel to the channel and exchanges heat with the cells by extending around of the circumference of the cylindrical cell and substantially extending between the two opposing end surfaces of the cell; a heat conductor that resides at least partially within the channel and exchanges heat with the interior surface of the cradle; and a heat exchanger that exchanges heat with the heat conductor, wherein the cradle, the heat conductor, and the heat exchanger cooperate to exchange heat between the cells and the heat exchanger.

Abstract: Disclosed is a method for management of a modular power source including the steps of setting a first operation threshold, selecting a module 10, retrieving data representative of the operating condition of the module 10, retrieving data representative of the time, storing the newly retrieved data, comparing the newly retrieved data to historical data representative of historical operating conditions of the module 10, determining a second operation threshold for the module 10 relative to the comparison, applying the second operation threshold for the module 10, and selecting the next module 10.

Abstract: In one embodiment, the invention includes a power source having a plurality of battery groups and a processor coupled to the groups and adapted to electrically disconnect a group from the power source. Each group includes a plurality of cells, a sensor adapted to sense operating parameters of the cells, and a protection circuit coupled to the sensor. In another embodiment, the invention includes a method of managing a power source with a two-tier approach. On a group level, the method includes retrieving cell data representative of the operating parameters of the cells of the group and managing the connection state of the group based on the retrieved cell data. On a system level, the method includes, retrieving group data representative of the operating parameters of the groups and managing the connection state of the group based on the retrieved group data.

Abstract: A shorter and a longer text string may be compared. Instead of simply comparing the characters only one character at a time, more than one character can be compared at a time. In addition, a null terminated string may be detected. The shorter strings may be handled differently than longer strings.

Abstract: Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface unit. The arbitration unit provides an interface to one or more I/O agents that issue atomic transactions to access and/or modify data stored in a shared memory space accessed via the memory interface unit. The host interface unit interfaces to a front-side bus (FSB) to which one or more processors may be coupled. In response to an atomic transaction issued by an I/O agent, the transaction is forked into two interdependent processes. Under one process, an inbound write transaction is injected into the host interface unit, which then drives the FSB to cause the processor(s) to perform a cache snoop. At the same time, an inbound read transaction is injected into the memory interface unit, which retrieves a copy of the data from the shared memory space.

Abstract: A method and apparatus to enable programmatic control of cache line eviction policies. A mechanism is provided that enables programmers to mark portions of code with different cache priority levels based on anticipated or measured access patterns for those code portions. Corresponding cues to assist in effecting the cache eviction policies associated with given priority levels are embedded in machine code generated from source- and/or assembly-level code. Cache architectures are provided that partition cache space into multiple pools, each pool being assigned a different priority. In response to execution of a memory access instruction, an appropriate cache pool is selected and searched based on information contained in the instruction's cue. On a cache miss, a cache line is selected from that pool to be evicted using a cache eviction policy associated with the pool. Implementations of the mechanism or described for both n-way set associative caches and fully-associative caches.

Abstract: In general, in one aspect, the disclosure describes a method that includes providing a memory access instruction of a processing element's instruction set including multiple parameters.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to data specified by a single instruction of a processing element specifying an access to data.