Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine observed failing bit patterns. Bit-reduction is performed on the observed failing bit patterns to construct first training samples. Using the first training samples, first-level machine-learning models are trained. Affine scan cell groups are identified. Second training samples are prepared for each of the affine scan cell groups by performing bit-filtering on a subset of the observed failing bit patterns associated with the faults being injected at scan cells in the each of the affine scan cell groups. Using the second training samples, second-level machine-learning models are trained. The first-level and second-level machine learning models can be applied in a multi-stage machine learning-based chain diagnosis process.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine observed failing bit patterns. Bit-reduction is performed on the observed failing bit patterns to construct first training samples. Using the first training samples, first-level machine-learning models are trained. Affine scan cell groups are identified. Second training samples are prepared for each of the affine scan cell groups by performing bit-filtering on a subset of the observed failing bit patterns associated with the faults being injected at scan cells in the each of the affine scan cell groups. Using the second training samples, second-level machine-learning models are trained. The first-level and second-level machine learning models can be applied in a multi-stage machine learning-based chain diagnosis process.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.