Abstract: An example apparatus is described for concurrent execution and copy of updated basic input/output system (“BIOS”) instructions. The apparatus may comprise a private serial peripheral interface and a processor to execute updated BIOS instructions. The apparatus may also comprise a controller to copy the updated BIOS instructions to the private serial peripheral interface. In various examples, execution and copy of the updated BIOS instructions may be performed concurrently.

Abstract: In an example, a system includes a firmware controller to initiate a SM execution mode of the system. The firmware controller scans memory for a process pool tag. The firmware controller compares the process pool tag to a set of operating system process pool tags and detects a coherency discrepancy between the process pool tag and the set of operating system process pool tags. The firmware controller exits the SM execution mode of the system.

Abstract: An example electronic device includes a storage circuit, a central processing unit (CPU) coupled to the storage circuit, and a controller coupled to the storage circuit. The CPU is to receive a Basic Input/Output System (BIOS) update image for the electronic device, verify a signature of the BIOS update image, and responsive to verification of the BIOS update image, store a portion of the BIOS update image in the storage circuit. The controller is to obtain the portion of the BIOS update image from the storage circuit, and program the portion of the BIOS update image to a BIOS component of the electronic device.

Abstract: An electronic device is described that may include an integrated circuit, a volatile memory coupled to the integrated circuit, a non-volatile memory controller coupled to the integrated circuit, and a non-volatile memory coupled to the non-volatile memory controller. In some examples, the integrated circuit is to receive a first instruction at a first frequency via a first storage access physical interface and receive a second instruction at a second frequency via a second storage access physical interface, wherein the first instruction and the second instruction are volatile memory access instructions. The integrated circuit may also be to arbitrate access to the volatile memory based on the first instruction and the second instruction and, responsive to the access to the volatile memory, synchronize contents of the volatile memory with the non-volatile memory via the non-volatile memory controller to maintain data coherency between the volatile memory and the non-volatile memory.

Abstract: In example implementations, a computing device is provided. The computing device includes a processor, a multiplexer, a first memory, a second memory, and a controller. The processor is to execute an operating system (OS). The multiplexer is coupled to the processor. The first memory is coupled to the multiplexer to store current basic input/output system (BIOS) instructions. The second memory is coupled to the multiplexer. The controller is coupled to the multiplexer to control connections of the multiplexer to allow the processor to store updated BIOS instructions in the second memory in a background while the OS is executed by processor.

Abstract: In some examples, executable code causes a processor to execute a first function and enter a system management mode responsive to receipt of a first system management interrupt during the execution of the first function. The executable code causes the processor to pause execution of the first function, save a state of the processor in the system management mode, and exit the system management mode. The executable code causes the processor to execute a second function identified by the first system management interrupt and receive a second system management interrupt to enter the system management mode. The executable code causes the processor to restore the state of the processor in the system management mode and exit the system management mode. The executable code causes the processor to resume execution of the first function after exiting the system management mode.

Abstract: In an example, an apparatus for access regulation of peripheral devices may include a processor and a communication interface to communicate to a peripheral device and to the processor. The processor may identify a pattern associated with receiving input data from a first peripheral device, wherein the pattern includes a keystroke rate, a delay in a keystroke pattern, a keystroke pressure, or a combination thereof. Similarly, the processor may, in response to detecting enumeration of a second peripheral device coupled to the apparatus, compare particular input data received from the second peripheral device with the pattern, and regulate access of the second peripheral device to the apparatus, based on the comparison.

Abstract: In an example, a system includes a firmware controller to initiate a SM execution mode of the system. The firmware controller scans memory for a process pool tag. The firmware controller compares the process pool tag to a set of operating system process pool tags and detects a coherency discrepancy between the process pool tag and the set of operating system process pool tags. The firmware controller exits the SM execution mode of the system.

Abstract: A build indicator is set in a build environment to a set value for building a program code, the set value selected from a first value indicating that a feature of the program code is enabled, and a second value indicating that the feature is disabled. In response to the set value of the build indicator being the first value, a variable is set to a value indicating that the feature is enabled. The program code is built using the value of the variable.

Abstract: A build indicator is set in a build environment to a set value for building a program code, the set value selected from a first value indicating that a feature of the program code is enabled, and a second value indicating that the feature is disabled. In response to the set value of the build indicator being the first value, a variable is set to a value indicating that the feature is enabled. The program code is built using the value of the variable.

Abstract: A build indicator is set in a build environment to a set value for building a program code, the set value selected from a first value indicating that a feature of the program code is enabled, and a second value indicating that the feature is disabled. In response to the set value of the build indicator being the first value, a variable is set to a value indicating that the feature is enabled. The program code is built using the value of the variable.

Abstract: A build indicator is set in a build environment to a set value for building a program code, the set value selected from a first value indicating that a feature of the program code is enabled, and a second value indicating that the feature is disabled. In response to the set value of the build indicator being the first value, a variable is set to a value indicating that the feature is enabled. The program code is built using the value of the variable.