Abstract: In certain aspects, an apparatus includes a first gating circuit having an input and an output, wherein the input of the first gating circuit is configured to receive a first clock signal. The apparatus also includes a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit. The apparatus further includes a control circuit configured to receive an enable signal, detect a logic state at the output of the delay circuit, and cause the first gating circuit to pass or gate the first clock signal based on the enable signal and the detected logic state at the output of the delay circuit.

Abstract: We developed a generic approach to type genome-wide single nucleotide polymorphisms in single human cells and to reconstruct for the first time genome-wide haplotypes of single- or dual-cell derived genotypes. Proof-of-principle is delivered for EBV-transformed lymphoblastoid cells as well as human blastomeres. To this end, multiple displacement amplified DNA samples of single cells were hybridized to Affymetrix 250K SNP-arrays. Different algorithmic designs were subsequently developed to assess from the single-cell derived SNP-probe intensities the sequence of syntenic alleles and to pinpoint accurately the majority of parental homologous recombination sites across the entire genome using a linkage-based approach. This included the development of algorithms that rectify a large part of the discrepant allelic assignments in raw single or dual-cell derived haplotypes. This method to infer genome-wide haplotypes from the analysis of only one or two cells has tremendous applicative value.

Abstract: Certain aspects are directed to a time-to-digital converter (TDC) that allows for a more accurate jitter measurement. The TDC generally includes a ring oscillator (RO) having a plurality of taps and configured to generate a plurality of RO signals at the plurality of taps, a counter having an input coupled to an oscillating node, and at least two sampling circuits, each having an input coupled to an output of the counter. In certain aspects, the at least two sampling circuits are configured to sample a count signal at the output of the counter based on at least two of the plurality of RO signals at the plurality of taps.

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

Abstract: An apparatus and method of employing mutually exclusive write and read clocks in scan capture mode for testing digital interfaces. The apparatus includes a first circuit and a first clock generator configured to generate a first clock signal for transferring a test sample from an input to an output of the first circuit in response to the first clock signal during each of a first set of scan capture cycles; a second circuit and a second clock generator configured to generate a second clock signal for transferring the test sample from an input to an output of the second circuit in response to the second clock signal during each of a second set of scan capture cycle; the first clock signal being suppressed during each scan capture cycle of the second set, and the second clock signal being suppressed during each scan capture cycle of the first set.

Abstract: The present invention provides a method for the analysis of genetic material of a subject, said method comprising: —obtaining continuous polymorphic variant allele frequency (PVAF) values of genetic material of a subject; —obtaining genotype information of a first and second parent; —categorizing the continuous PVAF values in a category corresponding to the first parent based on the genotype information of the first parent and second parent; —segmenting said categorized PVAF values; and —providing the segmented PVAF values to indicate a genetic anomaly in the genetic material of the subject and/or inheritance of the genetic material of the subject.

Abstract: We developed a generic approach to type genome-wide single nucleotide polymorphisms in single human cells and to reconstruct for the first time genome-wide haplotypes of single- or dual-cell derived genotypes. Proof-of-principle is delivered for EBV-transformed lymphoblastoid cells as well as human blastomeres. To this end, multiple displacement amplified DNA samples of single cells were hybridized to Affymetrix 250K SNP-arrays. Different algorithmic designs were subsequently developed to assess from the single-cell derived SNP-probe intensities the sequence of syntenic alleles and to pinpoint accurately the majority of parental homologous recombination sites across the entire genome using a linkage-based approach. This included the development of algorithms that rectify a large part of the discrepant allelic assignments in raw single or dual-cell derived haplotypes. This method to infer genome-wide haplotypes from the analysis of only one or two cells has tremendous applicative value.