Patents by Inventor Massimiliano Di Ventra

Massimiliano Di Ventra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180144239
    Abstract: Self-organizing logic gates formed from a combination of memristor devices and dynamic correction modules configured to provide a stable operation upon application of a signal to any terminal A SOLG of the invention can accept signals from any terminal and does not require an absence of signals at any other terminal. Terminal signals can superpose and the gate finds equilibrium, if an equilibrium exists.
    Type: Application
    Filed: July 12, 2016
    Publication date: May 24, 2018
    Applicant: The Regents of The University of California
    Inventors: Massimiliano Di Ventra, Fabio Lorenzo Traversa
  • Patent number: 9965586
    Abstract: Methods, systems, and devices are disclosed for processing macromolecule sequencing data with substantial noise reduction. In one aspect, a method for reducing noise in a sequential measurement of a macromolecule comprising serial subunits includes cross-correlating multiple measured signals of a physical property of subunits of interest of the macromolecule, the multiple measured signals including the time data associated with the measurement of the signal, to remove or at least reduce signal noise that is not in the same frequency and in phase with the systematic signal contribution of the measured signals.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: May 8, 2018
    Assignees: The Regents of the University of California, Los Alamos National Laboratory
    Inventors: Ivan K. Schuller, Massimiliano Di Ventra, Alexander Balatsky
  • Patent number: 9911080
    Abstract: Self-organizing logic gates formed from a combination of memristor devices and dynamic correction modules configured to provide a stable operation upon application of a signal to any terminal. A SOLG of the invention can accept signals from any terminal and does not require an absence of signals at any other terminal. Terminal signals can superpose and the gate finds equilibrium, if an equilibrium exists.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 6, 2018
    Assignee: The Regents of the University of California
    Inventors: Massimiliano Di Ventra, Fabio Lorenzo Traversa
  • Publication number: 20170316309
    Abstract: Self-organizing logic gates formed from a combination of memristor devices and dynamic correction modules configured to provide a stable operation upon application of a signal to any terminal. A SOLG of the invention can accept signals from any terminal and does not require an absence of signals at any other terminal. Terminal signals can superpose and the gate finds equilibrium, if an equilibrium exists.
    Type: Application
    Filed: July 10, 2017
    Publication date: November 2, 2017
    Inventors: Massimiliano Di Ventra, Fabio Lorenzo Traversa
  • Patent number: 9570140
    Abstract: A circuit utilizing memcapacitive elements for mixed memory storage and polymorphic computing is introduced. The circuit includes a plurality of memory cells each selectively or fixedly connected to a word line, bit line and dual bit line. Each memory cell includes a memcapacitive element. Voltage pulse generators can selectively applying voltage pulses to the memory cells. A method for mixed memory storage and polymorphic computing in at least two memory cells is provided. Data is stored by selectively applying voltage pulses to an individual memory cell to set an internal charge level of the memcapacitive element. Logic functions are conducted by applying voltage pulses having independent amplitudes to at least two memory cells to achieve internal charges in the memcapacitive elements of the cells to store an output bit according to a logic map that depends upon applied independent voltage pulse amplitudes.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: February 14, 2017
    Assignees: The Regents of the University of California
    Inventors: Massimiliano Di Ventra, Fabio Lorenzo Traversa, Yuriy V. Pershin
  • Publication number: 20160012876
    Abstract: A circuit utilizing memcapacitive elements for mixed memory storage and polymorphic computing is introduced. The circuit includes a plurality of memory cells each selectively or fixedly connected to a word line, bit line and dual bit line. Each memory cell includes a memcapacitive element. Voltage pulse generators can selectively applying voltage pulses to the memory cells. A method for mixed memory storage and polymorphic computing in at least two memory cells is provided. Data is stored by selectively applying voltage pulses to an individual memory cell to set an internal charge level of the memcapacitive element. Logic functions are conducted by applying voltage pulses having independent amplitudes to at least two memory cells to achieve internal charges in the memcapacitive elements of the cells to store an output bit according to a logic map that depends upon applied independent voltage pulse amplitudes.
    Type: Application
    Filed: March 7, 2014
    Publication date: January 14, 2016
    Inventors: Massimiliano Di Ventra, Fabio Lorenzo Traversa, Yuriy V. Pershin
  • Publication number: 20150347675
    Abstract: Methods, systems, and devices are disclosed for processing macromolecule sequencing data with substantial noise reduction. In one aspect, a method for reducing noise in a sequential measurement of a macromolecule comprising serial subunits includes cross-correlating multiple measured signals of a physical property of subunits of interest of the macromolecule, the multiple measured signals including the time data associated with the measurement of the signal, to remove or at least reduce signal noise that is not in the same frequency and in phase with the systematic signal contribution of the measured signals.
    Type: Application
    Filed: March 20, 2015
    Publication date: December 3, 2015
    Inventors: Ivan K. Schuller, Massimiliano Di Ventra, Alexander Balatsky
  • Patent number: 7235438
    Abstract: In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia. In another aspect, the present invention provides a silicon carbide semiconductor device that has a 4H-silicon carbide substrate, a layer of silicon dioxide disposed on the 4H-silicon carbide substrate and a region of substantial nitrogen concentration at the silicon dioxide/silicon carbide interface.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: June 26, 2007
    Assignees: Vanderbilt University, Auburn University
    Inventors: Gilyong Chung, Chin-Che Tin, John R. Williams, Kyle McDonald, Massimiliano Di Ventra, Robert A. Weller, Socrates T. Pantelides, Leonard C. Feldman
  • Patent number: 6939756
    Abstract: A method for manufacturing a silicon carbide semiconductor device. In one embodiment, the method includes the following steps: a layer of silicon dioxide is formed on a silicon carbide substrate to create a silicon dioxide/silicon carbide interface and then nitrogen is incorporated at the silicon dioxide/silicon carbide interface for reduction in an interface trap density. The silicon carbide substrate, in one embodiment, includes a n-type 4H-silicon carbide.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: September 6, 2005
    Assignees: Vanderbilt University, Auburn University
    Inventors: Gilyong Chung, Chin Che Tin, John R. Williams, Kyle McDonald, Massimiliano Di Ventra, Robert A. Weller, Sokrates T. Pantelides, Leonard C. Feldman