Patents by Inventor Massimiliano Mollichelli
Massimiliano Mollichelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9038044Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.Type: GrantFiled: December 5, 2013Date of Patent: May 19, 2015Assignee: MICRON TECHNOLOGY, INC.Inventors: Massimiliano Mollichelli, Andrea Martinelli, Stefan Schippers
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Publication number: 20140095774Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.Type: ApplicationFiled: December 5, 2013Publication date: April 3, 2014Applicant: Micron Technology Inc.Inventors: Massimiliano Mollichelli, Andrea Martinelli, Stefan Schippers
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Patent number: 8607210Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.Type: GrantFiled: November 30, 2010Date of Patent: December 10, 2013Assignee: Micron Technology, Inc.Inventors: Massimiliano Mollichelli, Andrea Martinelli, Stefan Schippers
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Publication number: 20120137049Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored n a trap address register.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: Micron Technology, Inc.Inventors: Massimiliano Mollichelli, Andrea Martinelli, Stefan Schippers
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Patent number: 7761675Abstract: A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.Type: GrantFiled: May 10, 2006Date of Patent: July 20, 2010Inventors: Francesco Mastroianni, Antonino Mondello, Elena Cussotto, Massimiliano Mollichelli, Mauro Sali
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Patent number: 7706193Abstract: A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell involved in a programming operation is detected, and at least a configuration signal of the regulator according to said detected operative condition is generated, this configuration signal taking a first and a second value associated with the first and second operation conditions.Type: GrantFiled: December 26, 2007Date of Patent: April 27, 2010Inventors: Davide Cascone, Nicola Del Gatto, Emanuele Confalonieri, Massimiliano Mollichelli
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Patent number: 7596023Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.Type: GrantFiled: November 2, 2007Date of Patent: September 29, 2009Inventors: Alessandro Magnavacca, Massimiliano Scotti, Nicola Del Gatto, Claudio Nava, Marco Ferrario, Massimiliano Mollichelli
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Patent number: 7515493Abstract: A sensing circuit is provided. The sensing circuit is adapted to determine when a cell current flowing trough a selected memory cell exceeds a reference current during an evaluation phase of a sensing operation. The sensing circuit is adapted to be coupled to at least one selected memory cell through a respective bit line. The sensing circuit includes: an access circuit node adapted to be coupled to the bit line; precharging circuitry adapted to be activated in a precharge phase of the sensing operation preceding the evaluation phase, so as to bring a voltage of said access circuit node to a reference voltage; a reference circuit node coupled to the access circuit node and arranged to receive the reference current.Type: GrantFiled: April 24, 2007Date of Patent: April 7, 2009Inventors: Umberto Di Vincenzo, Roberto Versari, Massimiliano Mollichelli
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Patent number: 7400281Abstract: A regulator for a digital-to-analog converter having in input a digital signal and suitable for providing an analog signal in output, the regulator including at least one pair of buffers having in input the digital signal and the outputs connected to a pair of circuit branches connected to the output of the regulator; each of the at least two circuit branches having at least one resistance. To at least one of the at least one pair of buffers a variable resistance is associated, and the regulator includes a circuit having in input the analog signal and adapted for measuring its waveform and acting on the variable resistance in response to its possible anomalous waveform compared to a desired waveform.Type: GrantFiled: March 2, 2007Date of Patent: July 15, 2008Assignee: STMicroelectronics, s.r.lInventors: Roberto Versari, Massimiliano Mollichelli, Nicola Del Gatto, Nicola Rosito, Emanuele Confalonieri
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Patent number: 7388793Abstract: A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell involved in a programming operation is detected, and at least a configuration signal of the regulator according to said detected operative condition is generated, this configuration signal taking a first and a second value associated with the first and second operation conditions.Type: GrantFiled: November 16, 2005Date of Patent: June 17, 2008Assignee: STMicroelectronics S.r.l.Inventors: Davide Cascone, Nicola Del Gatto, Emanuele Confalonieri, Massimiliano Mollichelli
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Publication number: 20080106937Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.Type: ApplicationFiled: November 2, 2007Publication date: May 8, 2008Applicant: STMicroelectronics S.r.I.Inventors: Alessandro MAGNAVACCA, Massimiliano Scotti, Nicola Del Gatto, Claudio Nava, Marco Ferrario, Massimiliano Mollichelli
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Publication number: 20080094906Abstract: A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell involved in a programming operation is detected, and at least a configuration signal of the regulator according to said detected operative condition is generated, this configuration signal taking a first and a second value associated with the first and second operation conditions.Type: ApplicationFiled: December 26, 2007Publication date: April 24, 2008Applicant: STMicroelectronics S.r.I.Inventors: Davide Cascone, Nicola Del Gatto, Emanuele Confalonieri, Massimiliano Mollichelli
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Patent number: 7324379Abstract: A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.Type: GrantFiled: September 30, 2005Date of Patent: January 29, 2008Assignee: STMicroelectronics S.r.l.Inventors: Nicola Del Gatto, Massimiliano Mollichelli, Massimiliano Scotti, Marco Sforzin
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Publication number: 20070285999Abstract: A sensing circuit is provided. The sensing circuit is adapted to determine when a cell current flowing trough a selected memory cell exceeds a reference current during an evaluation phase of a sensing operation. The sensing circuit is adapted to be coupled to at least one selected memory cell through a respective bit line. The sensing circuit includes: an access circuit node adapted to be coupled to the bit line; precharging circuitry adapted to be activated in a precharge phase of the sensing operation preceding the evaluation phase, so as to bring a voltage of said access circuit node to a reference voltage; a reference circuit node coupled to the access circuit node and arranged to receive the reference current.Type: ApplicationFiled: April 24, 2007Publication date: December 13, 2007Applicant: STMicroelectronics S.r.I.Inventors: Umberto Di Vincenzo, Roberto Versari, Massimiliano Mollichelli
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Publication number: 20070210949Abstract: A regulator for a digital-to-analog converter having in input a digital signal and suitable for providing an analog signal in output, the regulator including at least one pair of buffers having in input the digital signal and the outputs connected to a pair of circuit branches connected to the output of the regulator; each of the at least two circuit branches having at least one resistance. To at least one of the at least one pair of buffers a variable resistance is associated, and the regulator includes a circuit having in input the analog signal and adapted for measuring its waveform and acting on the variable resistance in response to its possible anomalous waveform compared to a desired waveform.Type: ApplicationFiled: March 2, 2007Publication date: September 13, 2007Applicant: STMICROELECTRONICS S.R.L.Inventors: Roberto Versari, Massimiliano Mollichelli, Nicola Del Gatto, Nicola Rosito, Emanuele Confalonieri
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Publication number: 20070016735Abstract: A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.Type: ApplicationFiled: May 10, 2006Publication date: January 18, 2007Applicant: STMicroelectronics S.r.I.Inventors: Francesco Mastroianni, Antonino Mondello, Elena Cussotto, Massimiliano Mollichelli, Mauro Sali
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Publication number: 20060171204Abstract: A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.Type: ApplicationFiled: September 30, 2005Publication date: August 3, 2006Applicant: STMicroelectronics S.r.I.Inventors: Nocola Del Gatto, Massimiliano Mollichelli, Massimiliano Scotti, Marco Sforzin
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Publication number: 20060133148Abstract: A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell involved in a programming operation is detected, and at least a configuration signal of the regulator according to said detected operative condition is generated, this configuration signal taking a first and a second value associated with the first and second operation conditions.Type: ApplicationFiled: November 16, 2005Publication date: June 22, 2006Applicant: STMicroelectronics S.r.l.Inventors: Davide Cascone, Nicola Del Gatto, Emanuele Confalonieri, Massimiliano Mollichelli