Abstract: A switching circuit is for switching an output thereof to one of a plurality of N input clock signals which are delayed relative to one another. The switching circuit includes at least one circuit responding to a control signal to enable the transmission, on an output signal, of a new signal of the plurality of input signals. The new signal is advanced or delayed relative to a current signal of the plurality of input signals which is currently transmitted on the output signal. The at least one circuit enables the transmission of the new signal before disabling the transmission of the current signal on the output signal. This substantially prevents the production of false signals during the switching of the output signal from one of the clock signals to another.

Abstract: Method for recovering a clock signal from an input data signal in a telecommunications system, that provides for comparing the input data signal with a recovered clock signal in order to control said recovered clock signal generation and provides for generating a plurality of delayed clock signals, obtained by multi-delaying at least a reference signal, said delayed clock signals being phase-shifted with respect to each other. According to the invention, said delayed clock signals show a phase shift with respect to each other, that is nominally constant in time, and, moreover, it is provided for selecting the recovered clock signal among said delayed clock signals.

Abstract: Disclosed is a method and network element for transporting Ethernet frames over a transport SDH/SONET network. at the sending point (AP#0), receiving a Ethernet frames to be transported through an Access Point (AP#0); mapping the Ethernet frames into a single Virtual Container (VC-X #) so that the transport of an Ethernet frame is performed by a single Virtual Container (VC); assigning a label/number to every frame; and at the receiving point (AP#1), re-ordering (FR) the received frames according to the assigned sequence label/number and outputting them through an Access Point (AP#1).

Abstract: Disclosed is a method for providing flow control of Ethernet frames transported over a transport SDH/SONET network. The method is characterized by comprising the following steps: at the network elements that host the sending and receiving points, providing termination blocks for storing queues of Ethernet frames, when the filling of termination block queue at the receiving node reaches a danger threshold, generating a Link Back-pressure Request and forwarding it to termination block at the transmitting node along the opposite direction; upon receipt of this request at the termination block suspending the transmission of other already stored Ethernet frames by until the disappearance of the Link Back-pressure Request.

Abstract: Method for recovering a clock signal from an input data signal in a telecommunications system, that provides for comparing the input data signal with a recovered clock signal in order to control said recovered clock signal generation and provides for generating a plurality of delayed clock signals, obtained by multi-delaying at least a reference signal, said delayed clock signals being phase-shifted with respect to each other. According to the invention, said delayed clock signals show a phase shift with respect to each other, that is nominally constant in time, and, moreover, it is provided for selecting the recovered clock signal among said delayed clock signals.

Abstract: A switching circuit is for switching an output thereof to one of a plurality of N input clock signals which are delayed relative to one another. The switching circuit includes at least one circuit responding to a control signal to enable the transmission, on an output signal, of a new signal of the plurality of input signals. The new signal is advanced or delayed relative to a current signal of the plurality of input signals which is currently transmitted on the output signal. The at least one circuit enables the transmission of the new signal before disabling the transmission of the current signal on the output signal. This substantially prevents the production of false signals during the switching of the output signal from one of the clock signals to another.