Abstract: A device for counteracting side-channel attacks (SCA), including a machine learning unit (MLU) that is connectable to a cryptographic core. The MLU includes: a feature extractor unit configured to extract selected information-sensitive signals from the cryptographic core and to generate machine learning features based on the selected information-sensitive signals; and a machine learning-based power estimator unit configured to output cumulative information-sensitive energy based on the generated machine learning features. The device further includes a power compensation unit that is configured to cancel out the cumulative information-sensitive energy so as to counteract side-channel attacks (SCA).

Abstract: A device for counteracting side-channel attacks (SCA), including a machine learning unit (MLU) that is connectable to a cryptographic core. The MLU includes: a feature extractor unit configured to extract selected information-sensitive signals from the cryptographic core and to generate machine learning features based on the selected information-sensitive signals; and a machine learning-based power estimator unit configured to output cumulative information-sensitive energy based on the generated machine learning features. The device further includes a power compensation unit that is configured to cancel out the cumulative information-sensitive energy so as to counteract side-channel attacks (SCA).

Abstract: A reconfigurable processor is described in an embodiment. The reconfigurable processor comprising a pipelined processor and memory modules associated with the pipelined processor, the pipelined processor being configured to execute an instruction set in a multi-stage pipeline including an instruction fetch (IF) stage, an instruction decode (ID) stage and an execute (EX) stage, wherein the pipelined processor is further adapted to perform each of the IF, ID and EX stages as two or more interleaved threads in a multi-thread mode and to share an IF pipeline output of the IF stage and/or an ID pipeline output of the ID stage between the two or more interleaved threads. A method of improving an efficiency of the reconfigurable processor is also described in an embodiment.

Abstract: Disclosed is a sensor fabric for detecting an attack on transistors. The fabric includes a plurality of sensor clusters. Each sensor cluster comprises a plurality of photodetectors and transistors, each photodetector being disposed next to a respective said transistor, a standard cell and an aggregator. The standard cell comprising a thresholding comparator for comparing a first input from a first group of the photodetectors of the respective cluster and a second input from a second group of the photodetectors of the respective cluster, the first input and second input being proportional to incident light sensed by the respective photodetectors, and flipping an output of the standard cell if a difference between the first input and second input exceeds a predetermined threshold. The aggregator aggregates the outputs from the clusters to produce an aggregated output, and triggering an alarm on detection of an attack based on the aggregated output.

Abstract: A method of generating true random numbers for use by a cryptographic hardware component for cryptographic algorithms or communication protocols, and a cryptographic hardware component for cryptographic algorithms or communication protocols. The method comprises the steps of controlling a clock pulsewidth, PW, for pulsed-latch clocking in the cryptographic hardware component to switch between using the cryptographic hardware component to generate the true random numbers in a first operating state; and using the cryptographic hardware component for cryptographic processing in a second operating state.

Abstract: Embedded memory structures and methods where an array of bitcells is interconnected by a plurality of bitlines and wordlines, each bitcell comprising a transistor connected to one of the wordlines and one of the bitlines. A TRNG circuit, peripheral to the array of bitcells, sets transistors connected to the one or more of the bitlines to an off state, determines a time interval between different crossing thresholds in a voltage discharge in the bitlines, and digitizes the time interval into bits of an TRNG output. A PUF circuit. peripheral to the array of bitcells, sets a pair of transistors connected to the pair of bitlines and the same wordline to an underdriven state, determines respective times of the transistors of the pair crossing a threshold in a voltage discharge in the pair of bitlines, and digitizes a time difference into an n-bit PUF output.

Abstract: A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system.

Abstract: A method of generating true random numbers for use by a cryptographic hardware component for cryptographic algorithms or communication protocols, and a cryptographic hardware component for cryptographic algorithms or communication protocols. The method comprises the steps of controlling a clock pulsewidth, PW, for pulsed-latch clocking in the cryptographic hardware component to switch between using the cryptographic hardware component to generate the true random numbers in a first operating state; and using the cryptographic hardware component for cryptographic processing in a second operating state.

Abstract: A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system.

Abstract: A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system.

Abstract: A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system.

Abstract: A method of providing a reference voltage for reading of a resistive memory array, and a read circuit for reading of a resistive memory array. The method comprises the steps of generating a first reference voltage when a bitline of the resistive memory array is in a first resistance state, and generating a second reference voltage when the bitline is in a second resistance state; wherein the first reference voltage is different from the first reference voltage and the first resistance state is different from the second resistance state.

Abstract: A method of providing a reference voltage for reading of a resistive memory array, and a read circuit for reading of a resistive memory array. The method comprises the steps of generating a first reference voltage when a bitline of the resistive memory array is in a first resistance state, and generating a second reference voltage when the bitline is in a second resistance state; wherein the first reference voltage is different from the first reference voltage and the first resistance state is different from the second resistance state.

Abstract: An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.

Abstract: An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.