Abstract: An integrated circuit having a plurality of sectors is disclosed. One embodiment includes a sector driver for simultaneously driving word lines corresponding to a single sector, the sector driver being connected to each word line and comprising a programmable sector memory for storing the sectors and word lines corresponding to each sector.

Abstract: An integrated circuit having a plurality of sectors is disclosed. One embodiment includes a sector driver for simultaneously driving word lines corresponding to a single sector, the sector driver being connected to each word line and comprising a programmable sector memory for storing the sectors and word lines corresponding to each sector.

Abstract: This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate having a first conductivity; a plurality of gate structures for storing charge in a non-volatile manner regularly arranged in above the surface of the semiconductor substrate and electrically isolated therefrom; a plurality of wordlines, each of the gate structures being connected to one of the wordlines and a group of the gate structures being connected to a common wordline; and a plurality of active regions, each of the active regions being individually connectable to at least one of the gate structures.

Abstract: This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate (1) having a first conductivity (p); a plurality of gate structures (CG1, FG1; . . . ; CGn, FGn) for storing charge in a non-volatile manner regularly arranged in above the surface of the semiconductor substrate (1) and electrically isolated therefrom; a plurality of wordlines (WL1-WL5), each of said gate structures (CG1, FG1; . . . ; CGn, FGn) being connected to one of said wordlines (WL1-WL5) and a group of said gate structures (CG1, FG1; . . . ; CGn, FGn) being connected to a common wordline (WL1-WL5); and a plurality of active regions (10, 20), each of said active regions (10, 20) being individually connectable to at least one of said gate structures (CG1, FG1; . . . ; CGn, FGn).

Abstract: A semiconductor memory device includes a semiconductor substrate having a first conductivity type and multiple parallel trenches extending in a first direction in the substrate. Each trench is filled with an isolation material and has an adjacent trench separated therefrom by a strip region. The device also includes multiple gate structures, for storing charge in a nonvolatile manner, arranged above the surface of the substrate and electrically isolated therefrom. The gate structures are arranged in parallel strips extending in a second direction that cross the strip regions. The device further includes multiple word lines, each of which is arranged on a corresponding gate structure from the multiple gate structures. The device also includes multiple active regions of a second conductivity type, each of which is arranged at one end of a corresponding strip region and each of which is electrically connectable to the gate structures of the corresponding strip region.

Abstract: A lateral DMOS transistor having a drain region which comprises a high-concentration portion with which the drain electrode is in contact and a low-concentration portion which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode in contact with a point of the low-concentration portion of the drain region which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

Abstract: A semiconductor memory device includes a semiconductor substrate having a first conductivity type and multiple parallel trenches extending in a first direction in the substrate. Each trench is filled with an isolation material and has an adjacent trench separated therefrom by a strip region. The device also includes multiple gate structures, for storing charge in a nonvolatile manner, arranged above the surface of the substrate and electrically isolated therefrom. The gate structures are arranged in parallel strips extending in a second direction that cross the strip regions. The device further includes multiple word lines, each of which is arranged on a corresponding gate structure from the multiple gate structures. The device also includes multiple active regions of a second conductivity type, each of which is arranged at one end of a corresponding strip region and each of which is electrically connectable to the gate structures of the corresponding strip region.

Abstract: A lateral DMOS transistor having a drain region which comprises a high-concentration portion with which the drain electrode is in contact and a low-concentration portion which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode in contact with a point of the low-concentration portion of the drain region which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.