Patents by Inventor Massimo Ceppi

Massimo Ceppi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10747633
    Abstract: Embodiments include apparatuses, methods, and systems for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. A gate level fault group is provided to include one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. A correlated RTL fault group is determined to be associated to a RTL circuit node, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Kevin Locker, Sai Ram Dheeraj Lokam, Siva Prasad Kota, Massimo Ceppi, Teo Cupaiuolo
  • Publication number: 20190050514
    Abstract: A method to perform a hybrid Register Transfer Level (RTL)/gate-level (GL) fault injection simulation of a hardware design comprises generating a list of one or more fault nodes in a GL netlist for the hardware design, mapping functionally equivalent comparison points between RTL logic for the hardware design and GL netlist of the hardware design, identifying a nearest set of downstream comparison points for one or more logic paths for the one or more fault nodes, identifying a nearest set of upstream comparison points for the one or more identified downstream comparison points, replacing RTL logic with equivalent GL netlist logic to provide hybrid RTL/GL netlist in code, and performing fault injection simulating using the hybrid RTL/GL netlist code
    Type: Application
    Filed: June 28, 2018
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: Massimo Ceppi, Teo Cupaiuolo, Mauro Pipponzi, Kevin Locker
  • Publication number: 20190050307
    Abstract: Embodiments include apparatuses, methods, and systems for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. A gate level fault group is provided to include one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. A correlated RTL fault group is determined to be associated to a RTL circuit node, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element. Other embodiments may also be described and claimed.
    Type: Application
    Filed: September 24, 2018
    Publication date: February 14, 2019
    Inventors: Kevin Locker, Sai Ram Dheeraj Lokam, Siva Prasad Kota, Massimo Ceppi, Teo Cupaiuolo