Patents by Inventor Massimo Ciacci
Massimo Ciacci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150172080Abstract: A proximity integrated circuit card bias adjustment. In one example, a decoding circuit, having an decoding range, for translating a data-frame signal having an information portion and a bias portion into an output code; and a bias adjust circuit coupled to receive the output code from the decoding circuit, and adjust the bias portion of the data-frame signal such that the output code is within the decoding range is disclosed. In another example, a method for proximity integrated circuit card bias adjustment, comprising: translating a data-frame signal having an information portion and a bias portion into an output code; and adjusting the bias portion of the data-frame signal such that the output code is within a decoding range is disclosed.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Applicant: NXP B.V.Inventors: Remco Cornelis Herman van de Beek, Massimo Ciacci, Ghiath Al-kadi
-
Patent number: 9038916Abstract: The invention proposes a smart card which comprises a digital signal processing receiver that can automatically identify the type of a smart card reader based on the error vector magnitude of signals received from the reader. The digital signal processing receiver is able to reconfigure itself at runtime in order to optimally minimize its power consumption in dependence on the type of reader it is communicating with. Furthermore, the invention proposes a new preamble structure that comprises a basic part and an optional additional part.Type: GrantFiled: October 4, 2011Date of Patent: May 26, 2015Assignee: NXP, B.V.Inventors: Ghiath Al-Kadi, Massimo Ciacci, Remco Cornelis Herman van de Beek
-
Patent number: 9008230Abstract: In one embodiment, an apparatus is provided that includes a first circuit configured and arranged to provide a modulated carrier signal in response to a signal provided from the antenna. The modulated carrier signal conveys data using peaks or amplitudes of the carrier signal. A second circuit is configured to rectify the modulated carrier signal and integrate the rectified signal in response to a first clock signal. A third circuit is coupled to an output of the second circuit and is configured to sample the integrated signal values and provide therefrom a sample-based approximation of the modulated carrier signal.Type: GrantFiled: January 8, 2013Date of Patent: April 14, 2015Assignee: NXP B.V.Inventors: Remco C. VandeBeek, Massimo Ciacci, Ghiath Al-kadi
-
Patent number: 8964904Abstract: Embodiments of a method for processing a baseband signal in a Direct Current (DC)-suppressed system, a system for processing a baseband signal in a DC-suppressed system, and a smart card are described. In one embodiment, a method for processing a baseband signal in a DC-suppressed system involves processing the baseband signal in the analog domain with a first high pass filter (HPF), converting the processed baseband signal to a digital signal, and processing the digital signal in the digital domain with a second HPF to provide a discrete-time differentiation of the baseband signal. Other embodiments are also described.Type: GrantFiled: January 7, 2013Date of Patent: February 24, 2015Assignee: NXP B.V.Inventors: Massimo Ciacci, Remco Cornelis Herman van de Beek, Ghiath Al-Kadi
-
Patent number: 8928401Abstract: Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain.Type: GrantFiled: November 26, 2012Date of Patent: January 6, 2015Assignee: NXP, B.V.Inventors: Jos Verlinden, Remco van de Beek, Massimo Ciacci
-
Patent number: 8842720Abstract: The method comprises receiving an input stream of symbols (x(i)) representing a phase change and magnitude of an RF signal, the magnitudes of the symbols are constant, the phase changes of the symbols encode digital information, and adjust the input stream of symbols to reduce inter-symbol interference. The adjusting iteratively determines a next symbol of the equalized stream (x?(n)) after receiving a next symbol of the input stream (x(n)) by multiplying the next symbol of the input stream (x(n)) with a next adjusting real number (a(n)), multiplying a previous symbol of the input stream (x(n?1)) with a previous adjusting real number (a(n?1)), the previous symbol being received before the next symbol of the input stream, and the next symbol of the equalized stream is computed from the multiplied next symbol and the multiplied previous symbol of the input stream.Type: GrantFiled: June 27, 2013Date of Patent: September 23, 2014Assignee: NXP B.V.Inventors: Remco Cornelis Herman van de Beek, Massimo Ciacci, Jos Verlinden, Ghaith Al-kadi
-
Patent number: 8781051Abstract: A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit.Type: GrantFiled: March 12, 2012Date of Patent: July 15, 2014Assignee: NXP, B.V.Inventors: Massimo Ciacci, Remco Cornelis Herman van de Beek, Ghiath Al-kadi
-
Publication number: 20140192934Abstract: Embodiments of a method for processing a baseband signal in a Direct Current (DC)-suppressed system, a system for processing a baseband signal in a DC-suppressed system, and a smart card are described. In one embodiment, a method for processing a baseband signal in a DC-suppressed system involves processing the baseband signal in the analog domain with a first high pass filter (HPF), converting the processed baseband signal to a digital signal, and processing the digital signal in the digital domain with a second HPF to provide a discrete-time differentiation of the baseband signal. Other embodiments are also described.Type: ApplicationFiled: January 7, 2013Publication date: July 10, 2014Applicant: NXP B.V.Inventors: Massimo Ciacci, Remco Cornelis Herman van de Beek, Ghiath Al-Kadi
-
Publication number: 20140192931Abstract: In one embodiment, an apparatus is provided that includes a first circuit configured and arranged to provide a modulated carrier signal in response to a signal provided from the antenna. The modulated carrier signal conveys data using peaks or amplitudes of the carrier signal. A second circuit is configured to rectify the modulated carrier signal and integrate the rectified signal in response to a first clock signal. A third circuit is coupled to an output of the second circuit and is configured to sample the integrated signal values and provide therefrom a sample-based approximation of the modulated carrier signal.Type: ApplicationFiled: January 8, 2013Publication date: July 10, 2014Applicant: NXP B.V.Inventors: Remco C. VandeBeek, Massimo Ciacci, Ghiath Al-kadi
-
Publication number: 20140145787Abstract: Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain.Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: NXP B.V.Inventors: Jos Verlinden, Remco van de Beek, Massimo Ciacci
-
Publication number: 20140038534Abstract: Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic.Type: ApplicationFiled: August 1, 2012Publication date: February 6, 2014Inventors: Massimo Ciacci, Jos Verlinden, Remco van de Beek
-
Publication number: 20140003484Abstract: A method for pre-equalizing a digital modulated RF signal is presented. The method comprises receiving an input stream of symbols (x(i)) representing a phase change and magnitude of an RF signal, the magnitudes of the symbols in the input stream are constant, the phase changes of the symbols in the input stream encode digital information, and adjusting the input stream of symbols to reduce inter-symbol interference in transmission of an RF signal modulated according to the input stream, thus obtaining an equalized stream of symbols (x?(i)), each symbol of the equalized stream representing a phase change and magnitude of an RF signal.Type: ApplicationFiled: June 27, 2013Publication date: January 2, 2014Inventors: Remco Cornelis Herman van de Beek, Massimo Ciacci, Jos Verlinden, Ghiath Al-kadi
-
Publication number: 20130064271Abstract: Equalization circuits and methods are implemented for a variety of applications. According to one such application, a transmitting device wirelessly communicates using an antenna. The device has a transmission circuit that is configured and arranged to transmit a first wireless signal using magnetic coupling between the antenna and a remote device, the coupling occurring over a wireless medium. A receiver circuit of the transmitting device is configured and arranged to receive a second wireless signal that is from the antenna and that represents the first wireless signal as modified by the coupling occurring over the wireless medium. An error circuit of the device is configured and arranged to generate an error signal by comparing the first wireless signal to the second wireless signal. An equalizer circuit of the device is configured and arranged to pre-code the first wireless signal with coding that compensates for inter-symbol interference by compensating for the error signal.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Inventors: Remco Cornelis Herman van de Beek, Massimo Ciacci
-
Patent number: 8378710Abstract: Various embodiments relate to an anti-tampering circuit for a secure device including: a signal delay detector; a clock delay detector; a clock duty cycle detector; and a protection unit that receives an error indication from the signal delay detector, clock delay detector, and the clock duty cycle detector, wherein the protection unit indicates tampering to a secure device upon receiving the error indication.Type: GrantFiled: September 20, 2011Date of Patent: February 19, 2013Assignee: NXP B.V.Inventors: Ghiath Al-Kadi, Jan Hoogerbrugge, Massimo Ciacci
-
Publication number: 20120269304Abstract: A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit.Type: ApplicationFiled: March 12, 2012Publication date: October 25, 2012Applicant: NXP B.V.Inventors: Massimo Ciacci, Remco Cornelis Herman Van De Beek, Ghiath Al-kadi
-
Publication number: 20120080529Abstract: The invention proposes a smart card which comprises a digital signal processing receiver that can automatically identify the type of a smart card reader based on the error vector magnitude of signals received from the reader. The digital signal processing receiver is able to reconfigure itself at runtime in order to optimally minimize its power consumption in dependence on the type of reader it is communicating with. Furthermore, the invention proposes a new preamble structure that comprises a basic part and an optional additional part.Type: ApplicationFiled: October 4, 2011Publication date: April 5, 2012Applicant: NXP B.V.Inventors: Ghiath Al-Kadi, Massimo Ciacci, Remco Cornelis Herman van de Beek
-
Publication number: 20080232213Abstract: On existing DVD and CD players a control loop is required for the adaptation and timing recovery. For Two-Dimensional Optical Storage such a control loop has drawbacks because PRML detection in the form of a stripe-wise Viterbi detector is used. Such a detector introduces an increasing detection delay when going from the outer rows towards the center of the broad spiral. A feedback loop is arranged to determining an error signal from a first area of the data block where the first area is that area where the error signal can be determined within the shortest period of time. This reduces the duration of the detection step and thus increases the stability of the control loop.Type: ApplicationFiled: January 24, 2005Publication date: September 25, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONIC, N.V.Inventors: Johannes Wilhelmus Maria Bergmans, Albert Hendrik Jan Immink, Jamal Riani, Willem Marie Julia Marcel Coene, Steven Jena-Marie Lucie Van Beneden, Massimo Ciacci, Ali Nowbakht Irani
-
Patent number: 7120277Abstract: A method of determining segments in a series of images based on previous segmentation results and on motion estimation. A second segment (108) of a second image (106) is determined based on a first segment (102) of a first image (100), with the first segment (102) and the second segment (108) corresponding to one object (104). The method comprises a calculation step to compare values of pixels of the first image (100) and the second image (106) in order to calculate a motion model which defines the transformation of the first segment (102) into the second segment (108). An example of such a motion model allows only translation. Translation can be described with one motion vector (110).Type: GrantFiled: May 14, 2002Date of Patent: October 10, 2006Assignee: Koninklijke Philips Electronics N.V.Inventors: Anna Pelagotti, Gerard Anton Lunter, Massimo Ciacci
-
Publication number: 20030035583Abstract: A method of determining segments in a series of images based on previous segmentation results and on motion estimation. A second segment (108) of a second image (106) is determined based on a first segment (102) of a first image (100), with the first segment (102) and the second segment (108) corresponding to one object (104). The method comprises a calculation step to compare values of pixels of the first image (100) and the second image (106) in order to calculate a motion model which defines the transformation of the first segment (102) into the second segment (108). An example of such a motion model allows only translation. Translation can be described with one motion vector (110).Type: ApplicationFiled: May 14, 2002Publication date: February 20, 2003Inventors: Anna Pelagotti, Gerard Anton Lunter, Massimo Ciacci