Patents by Inventor Massimo Fidone

Massimo Fidone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Phase-change memory device with drive circuit
    Patent number: 10658032
    Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: May 19, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cesare Torti, Fabio Enrico Carlo Disegni, Davide Manfré, Massimo Fidone
  • Phase-Change Memory Device with Drive Circuit
    Publication number: 20190043574
    Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
    Type: Application
    Filed: October 9, 2018
    Publication date: February 7, 2019
    Inventors: Cesare Torti, Fabio Enrico Carlo Disegni, Davide Manfré, Massimo Fidone
  • Phase-change memory device with drive circuit
    Patent number: 10115460
    Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 30, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cesare Torti, Fabio Enrico Carlo Disegni, Davide Manfre′, Massimo Fidone
  • PHASE-CHANGE MEMORY DEVICE WITH DRIVE CIRCUIT
    Publication number: 20180151223
    Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
    Type: Application
    Filed: June 30, 2017
    Publication date: May 31, 2018
    Inventors: Cesare Torti, Fabio Enrico Carlo Disegni, Davide Manfre', Massimo Fidone