Patents by Inventor Massimo Fonte

Massimo Fonte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Minimum-size belief propagation network for FEC iterative encoders and decoders and related routing method
    Patent number: 11526396
    Abstract: The invention relates to an interconnection network for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. Each stage includes switching elements having input pins and output pins. The input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals. The input and output pins of the switching elements of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: December 13, 2022
    Assignee: Thales Alenia Space Italia S.p.A. Con Unico Socio
    Inventors: Domenico Giancristofaro, Massimo Fonte
  • Minimum-Size Belief Propagation Network for FEC Iterative Encoders and Decoders and Related Routing Method
    Publication number: 20200081766
    Abstract: The invention relates to an interconnection network for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. Each stage includes switching elements having input pins and output pins. The input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals. The input and output pins of the switching elements of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage.
    Type: Application
    Filed: May 11, 2018
    Publication date: March 12, 2020
    Applicant: Thales Alenia Space Italia S.p.A. Con Unico Socio
    Inventors: Domenico Giancristofaro, Massimo Fonte