Abstract: A boost DC-DC converter includes a switching network, coupled to an inductor, controlled by a PWM driving signal. A control loop receives a voltage output and provides the PWM driving signal. The control loop generates an error signal as a function of a difference between voltage output voltage and a reference, with the PWM driving signal generated based on the error signal. A low pass filter circuit within the control loop receives the PWM driving signal and provides at least one filtered signal. An adder node of the control loop receives the at least one filtered signal from the low pass filter circuit for addition to the at least one filtered signal. The PWM driving signal is generated as a function of a sum of the filtered signal and the error signal.

Abstract: In a multi-level hybrid DC-DC converter with a flying capacitor, a feedback circuit includes a first oscillator and produces a first clock signal with a frequency dependent on an output voltage. A second oscillator produces a second clock signal having a frequency dependent on a reference voltage. A logic circuit switches, as a function of the first and second clock signals, connection of the flying capacitor between one state where the flying capacitor is connected between an input node and a switching node, and another state where the capacitor is connected between the switching node and a ground node. The duty cycle of the first/second clock signal varies so that when the flying capacitor voltage is lower than a target voltage a duration of the one state is increased, and when the flying capacitor voltage is higher than the target voltage a duration of the another state is increased.

Abstract: A Single Input Dual Output converter includes a first switch coupling an input to a first inductor terminal, a second switch coupling a second inductor terminal to ground, a third switch coupling the second inductor terminal to a positive output, and a fourth switch coupling the first inductor terminal to a negative output. During time-shared control, the negative and positive outputs are independently served by conversion cycles. Each conversion cycle includes: a positive phase with a positive charge phase (closing only the first and second switches), followed by an additional phase (closing only the first and third switches for a given time duration), and followed by a positive discharge phase (closing only the third and fourth switches). Each conversion cycle further includes a negative phase with a negative charge phase (closing only the first and second switches) followed by a negative discharge phase (closing only the second and fourth switches).

Abstract: A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.

Abstract: A method controls a Full Bridge converter with a Current-Doubler of the type including at least a first and a second half-bridges of diodes connected to respective control transistors. The method includes detecting a reference value, comparing, instant by instant, the reference value with an output voltage value of the converter, and carrying out a switching from a transfer phase to an energy recirculation phase in correspondence with instants when the output voltage value reaches the reference value.

Abstract: A method controls a Full Bridge converter with a Current-Doubler of the type including at least a first and a second half-bridges of diodes connected to respective control transistors. The method includes detecting a reference value, comparing, instant by instant, the reference value with an output voltage value of the converter, and carrying out a switching from a transfer phase to an energy recirculation phase in correspondence with instants when the output voltage value reaches the reference value.

Abstract: Photodetector device comprising a semiconductor substrate (1) of a first type of conductivity connected to a first electrode (2). Said substrate comprises an active area (4) made up of different semiconductor regions of a second type of conductivity (8, 9, 10) insulated from each other and connected to respective second electrodes (13, 14, 15) so that each of them can be connected separately from the others to an appropriate bias voltage. By regulating the bias voltages applied to these regions the function of optic diaphragm of the device can be controlled. The device works without needing any form of optical insulation between the different regions of the active area and always uses the same single output electrode for the signal in all the different situations of diaphragm adjustment.

Abstract: A voltage regulator includes an input terminal adapted for being coupled to an input voltage and an output terminal adapted for being coupled to a load. The voltage regulator includes a first switch adapted for selectively coupling to the input terminal and to the output terminal, a current sensor for measuring an output current flowing towards the output terminal, a voltage sensor for measuring the output voltage from the output terminal, and a digital controller which drives the first switch. The controller closes the first switch when the error voltage is less than a first preset value of voltage and opens the first switch when the output current is greater than a first preset value of current.

Abstract: A voltage regulator includes an input terminal adapted for being coupled to an input voltage and an output terminal adapted for being coupled to a load. The voltage regulator includes a first switch adapted for selectively coupling to the input terminal and to the output terminal, a current sensor for measuring an output current flowing towards the output terminal, a voltage sensor for measuring the output voltage from the output terminal, and a digital controller which drives the first switch. The controller closes the first switch when the error voltage is less than a first preset value of voltage and opens the first switch when the output current is greater than a first preset value of current.

Abstract: Photodetector device comprising a semiconductor substrate (1) of a first type of conductivity connected to a first electrode (2). Said substrate comprises an active area (4) made up of different semiconductor regions of a second type of conductivity (8, 9, 10) insulated from each other and connected to respective second electrodes (13, 14, 15) so that each of them can be connected separately from the others to an appropriate bias voltage. By regulating the bias voltages applied to these regions the function of optic diaphragm of the device can be controlled. The device works without needing any form of optical insulation between the different regions of the active area and always uses the same single output electrode for the signal in all the different situations of diaphragm adjustment.

Abstract: It is an integrated circuit capable of determining the quenching and the reset of an avalanche photodiode operating in Geiger mode so as to detect single photons falling on the surface of said photodiode. The circuit scheme used makes possible to reduce the size of the circuit down to a single semiconductor chip, to reduce the power dissipation and to reduce the cost of the circuit, at the same time keeping the performance at good level.

Abstract: A method for digital-to-analog conversion of a digital input code into a first output analog signal and a second output analog signal to be supplied to a first terminal and a second terminal, respectively, of an audio load, the conversion being performed by means of a DAC with N-level balanced output, the conversion method includes using N/2 positive generator elements supplying respective positive elementary contributions which are nominally equal to one another, and N/2 negative generator elements supplying respective negative elementary contributions which are nominally equal to one another and, in absolute value, equal to the positive elementary contributions; attributing the same progressive addresses to the positive generator elements and to the negative generator elements; defining a first index for the positive input codes and a second index for the negative input codes; and, in the presence of an input code at the input of the DAC, selecting between the first index and the second index, the index cor

Abstract: A method for digital-to-analog conversion of a digital input code into a first output analog signal and a second output analog signal to be supplied to a first terminal and a second terminal, respectively, of an audio load, the conversion being performed by means of a DAC with N-level balanced output, the conversion method includes using N/2 positive generator elements supplying respective positive elementary contributions which are nominally equal to one another, and N/2 negative generator elements supplying respective negative elementary contributions which are nominally equal to one another and, in absolute value, equal to the positive elementary contributions; attributing the same progressive addresses to the positive generator elements and to the negative generator elements; defining a first index for the positive input codes and a second index for the negative input codes; and, in the presence of an input code at the input of the DAC, selecting between the first index and the second index, the index cor

Abstract: The invention concerns an output circuit for extracting the avalanche pulse produced by an avalanche photodiode for single photon detection (Single Photon Avalanche Diode, SPAD), which makes possible to detect and measure with the best possible precision the time of arrival of an incident photon on the surface of said SPAD. The circuit is built with a coupling network, connected to a terminal of said SPAD biased at high voltage and a comparator. Said network is designed so that the differentiation time constant, introduced by said block, is less than the total duration of the avalanche current pulse, but longer than the risetime of said pulse (FIG. 5 and FIG. 8). The circuit object of the invention has the virtue of being usable in all the circuit configurations for avalanche quenching in SPADs described in the technical and scientific literature.

Abstract: The invention concerns an output circuit for extracting the avalanche pulse produced by an avalanche photodiode for single photon detection (Single Photon Avalanche Diode, SPAD), which makes possible to detect and measure with the best possible precision the time of arrival of an incident photon on the surface of said SPAD. The circuit is built with a coupling network, connected to a terminal of said SPAD biased at high voltage and a comparator. Said network is designed so that the differentiation time constant, introduced by said block, is less than the total duration of the avalanche current pulse, but longer than the risetime of said pulse (FIG. 5 and FIG. 8). The circuit object of the invention has the virtue of being usable in all the circuit configurations for avalanche quenching in SPADs described in the technical and scientific literature.

Abstract: Silicon-VLSI-compatible photodetectors, in the form of a metal-semiconductor-metal photodetector (MSM-PD) or a lateral p-i-n photodetector (LPIN-PD), are disclosed embodying interdigitated metallic electrodes on a silicon surface. The electrodes of the MSM-PD have a moderate to high electron and hole barrier height to silicon, for forming the Schottky barriers, and are fabricated so as to be recessed in the surface semiconducting layer of silicon through the use of self-aligned metallization either by selective deposition or by selective reaction and etching, in a manner similar to the SALICIDE concept. Fabrication is begun by coating the exposed Si surface of a substrate with a transparent oxide film, such that the Si/oxide interface exhibits low surface recombination velocity.