Patents by Inventor Massimo Grasso

Massimo Grasso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220020843
    Abstract: A multi-voltage domain device includes a semiconductor layer including a first voltage domain, a second voltage domain, and an isolation region that electrically isolates the first voltage domain and the second voltage domain in a lateral direction. The isolation region includes at least one deep trench isolation barrier. A layer stack is arranged on the semiconductor layer and includes a stack insulator layer, a first coil arranged in the stack insulator layer, and a second coil arranged in the stack insulator layer and laterally separated from the first coil in the lateral direction. The first and second coils are magnetically coupled to each other in the lateral direction. The first coil includes terminals arranged vertically over the first region and are electrically coupled to the first voltage domain, and the second coil includes terminals arranged vertically over the second region and are electrically coupled to the second voltage domain.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 20, 2022
    Applicant: Infineon Technologies Austria AG
    Inventor: Massimo GRASSO
  • Patent number: 10862483
    Abstract: A gate driver includes a high-side region that operates in a first voltage domain, a low-side region that operations in a second voltage domain lower than the first voltage domain, a termination region interposed between the high-side region and the low-side region and configured to isolate the first voltage domain from the second voltage domain, a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor, a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor, and a plurality of termination diodes disposed in the termination region and configured to transmit information bits between the high-side region and the low-side region, where each of the plurality of termination diodes includes an anode coupled to the low-side region and a cathode coupled to the high-side region.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: December 8, 2020
    Inventors: Amedeo Paganini, Massimo Grasso, Sergio Morini, Davide Respigo
  • Publication number: 20200244265
    Abstract: A gate driver includes a high-side region that operates in a first voltage domain, a low-side region that operations in a second voltage domain lower than the first voltage domain, a termination region interposed between the high-side region and the low-side region and configured to isolate the first voltage domain from the second voltage domain, a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor, a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor, and a plurality of termination diodes disposed in the termination region and configured to transmit information bits between the high-side region and the low-side region, where each of the plurality of termination diodes includes an anode coupled to the low-side region and a cathode coupled to the high-side region.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 30, 2020
    Applicant: Infineon Technologies Austria AG
    Inventors: Amedeo PAGANINI, Massimo GRASSO, Sergio MORINI, Davide RESPIGO
  • Patent number: 9473043
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 18, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Patent number: 9257983
    Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: February 9, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Min Fang, Massimo Grasso, Niraj Ranjan
  • Publication number: 20150207432
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Application
    Filed: March 31, 2015
    Publication date: July 23, 2015
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Patent number: 9000829
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 7, 2015
    Assignee: International Rectifier Corporation
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Patent number: 8988128
    Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit. The high voltage circuit is configured to receive the differential signal from the low voltage circuit so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The differential signal is provided by the low voltage circuit responsive to a feedback signal from the high voltage circuit. The feedback signal can indicate common mode noise in the level shifter. Furthermore, the low voltage circuit can be configured to refresh the differential signal responsive to the feedback signal.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventors: Min Fang, Massimo Grasso, Niraj Ranjan
  • Publication number: 20150054564
    Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Inventors: Min Fang, Massimo Grasso, Niraj Ranjan
  • Patent number: 8878591
    Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: November 4, 2014
    Assignee: International Rectifier Corporation
    Inventors: Min Fang, Massimo Grasso, Niraj Ranjan
  • Publication number: 20140028371
    Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit. The high voltage circuit is configured to receive the differential signal from the low voltage circuit so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The differential signal is provided by the low voltage circuit responsive to a feedback signal from the high voltage circuit. The feedback signal can indicate common mode noise in the level shifter. Furthermore, the low voltage circuit can be configured to refresh the differential signal responsive to the feedback signal.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 30, 2014
    Inventors: Min Fang, Massimo Grasso, Niraj Ranjan
  • Publication number: 20140028369
    Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 30, 2014
    Inventors: Min Fang, Massimo Grasso, Niraj Ranjan
  • Publication number: 20130271201
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Application
    Filed: March 11, 2013
    Publication date: October 17, 2013
    Applicant: International Rectifier Corporation
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Patent number: 8013612
    Abstract: An integrated ground fault detection circuit in accordance with an embodiment of the present application includes a shunt resistor provided on a positive rail of a DC bus, a high voltage pocket including a sensory circuit connected to the shunt resistor and operable to detect a fault condition indicating a short circuit and a transmitter section operable to continuously transmit a fault condition signal indicating the fault condition and a low voltage pocket including a receiver operable to receive the fault condition signal from the sensory circuit and a logic unit, connected to the receiver, and operable to provide a fault output signal indicating the presence of a fault condition based on the fault condition signal.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: September 6, 2011
    Assignee: International Rectifier Corporation
    Inventors: Sergio Morini, Marco Giandalia, David Respigo, Stefano Ruzza, Massimo Grasso
  • Patent number: 7864018
    Abstract: A planar transformer arrangement and method provide isolation between an input signal and an output signal.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: January 4, 2011
    Assignee: International Rectifier Corporation
    Inventors: Marco Giandalia, Massimo Grasso, Marco Passoni
  • Patent number: 7719223
    Abstract: A circuit for indirectly measuring a sign of a current flowing in an inverter stage coupled to a phase of a motor or indirectly measuring the sign of the voltage induced by a counter Electromotive Force (EMF) in a coil of the phase of the motor, the inverter stage being connected between a power supply and the ground. The circuit includes a gate driver circuit coupled to the inverter stage for alternatively connecting the phase of the motor to the power supply and to ground, the gate driver circuit having a current sign detection circuit, wherein the current sign detection circuit senses the sign of the current flowing in the inverter stage, or the sign of the counter EMF for controlling the commutation of switches in the inverter stage.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: May 18, 2010
    Assignee: International Rectifier Corporation
    Inventors: Massimo Grasso, Andrea (Francesco) Merello, Christian Locatelli
  • Patent number: 7619450
    Abstract: A startup circuit for providing a startup voltage from a high voltage DC bus voltage to an application circuit, the startup circuit comprising an integrated circuit package for at least a control circuit for driving at least one power switch of the application circuit having a low voltage terminal; a dropping resistor in the integrated circuit package having a first terminal for coupling to the high voltage DC bus and a second terminal, the dropping resistor dropping the high voltage DC bus voltage to a reduced voltage and providing the reduced voltage at the second terminal; further comprising a low voltage regulator coupled to the second terminal for using the reduced voltage for enabling generation of a regulated startup low voltage DC output at a preset level at the low voltage terminal for powering at least one part of the application circuit during startup of the application circuit, wherein the high voltage DC bus voltage is the only voltage source provided externally to the integrated circuit package.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: November 17, 2009
    Assignee: International Rectifier Corporation
    Inventors: Massimo Grasso, Sergio Morini
  • Patent number: 7554276
    Abstract: A safety circuit for providing protection against failures that impact safety of an inverter circuit driving a Permanent Magnet Synchronous Motor (PMSM) including high and low side switches connected in a bridge and driven by a gate driver circuit during operation of the PMSM in a field weakening mode, the gate driver circuit including stages for driving the high and low side switches, the safety circuit comprising a main power supply and a back-up power supply for supplying voltage to the gate driver circuit driving the switches of the bridge of the inverter circuit, wherein if the main power supply fails to deliver adequate power to the gate driver circuit, the back-up power supply provides power to the gate driver circuit to allow the gate driver circuit to turn ON the low side switches and turn OFF the high side switches.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: June 30, 2009
    Assignee: International Rectifier Corporation
    Inventors: Giovanni Galli, Massimo Grasso, Cesare Bocchiola
  • Publication number: 20090102488
    Abstract: An integrated ground fault detection circuit in accordance with an embodiment of the present application includes a shunt resistor provided on a positive rail of a DC bus, a high voltage pocket including a sensory circuit connected to the shunt resistor and operable to detect a fault condition indicating a short circuit and a transmitter section operable to continuously transmit a fault condition signal indicating the fault condition and a low voltage pocket including a receiver operable to receive the fault condition signal from the sensory circuit and a logic unit, connected to the receiver, and operable to provide a fault output signal indicating the presence of a fault condition based on the fault condition signal.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 23, 2009
    Applicant: International Rectifier Corporation
    Inventors: Sergio Morini, Marco Giandalia, Davide Respigo, Stefano Ruzza, Massimo Grasso
  • Patent number: 7474069
    Abstract: A circuit for optimizing power transferred from an inverter circuit to a motor, the circuit using an open loop method to start-up the motor and have it reach a minimum speed, each phase of the motor receiving voltage from the inverter circuit.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: January 6, 2009
    Assignee: International Rectifier Corporation
    Inventors: Marco Palma, Massimo Grasso