Abstract: This invention relates to a memory cell which comprises a capacitor having a first electrode and a second electrode separated by a dielectric layer. Such dielectric layer comprises a layer of a semi-insulating material which is fully enveloped by an insulating material and in which an electric charge is permanently present or trapped therein. Such electric charge accumulated close to the first or to the second electrode, depending on the electric field between the electrodes, thereby defining different logic levels.

Abstract: In order to obtain an EPROM memory array with high compactness and the possibility of asymmetrically doping the channel, an array is proposed which comprises a substrate having a first conductivity type, first and second bit lines having the opposite conductivity type and extending parallel and mutually alternated in the substrate, a plurality of thick insulating material regions extending at least partially in the substrate above and parallel to the first bit lines, a plurality of floating gate regions extending above the substrate perpendicular to and between adjacent pairs of bit lines, a plurality of word lines extending perpendicular to the bit lines and above, but electrically insulated from, the floating gate regions, wherein the second bit lines extend up to the surface of the substrate and define unburied bit lines to the side whereof it is possible to provide enriched channel regions. The unburied bit lines can furthermore be subjected to a siliciding process to reduce series resistance.

Abstract: A process for fabricating an integrated memory matrix of EPROM cells having a "tablecloth" organization, with source and drain lines parallel among each other and running between parallel strips of isolating field oxide, floating gate structures formed between said source and drain lines and control gate lines running parallel among each other and perpendicularly to said source and drain lines and over said floating gate structures, utilizes a mask through which a stack, formed by a second level polysilicon layer, an interpoly isolating dielectric layer, a first level polysilicon layer and a gate oxide layer, is etched for defining in a longitudinal sense the gate structures (i.e. the channel length) of the EPROM cells. The gate structures are subsequently defined in a transversal sense by etching through another mask a stack comprising a third level polysilicon layer deposited directly over said second level polysilicon layer, said interpoly dielectric layer and said first level polysilicon layer.

Abstract: The UPROM memory cell comprises self-aligned lines of source and lines of drain obtained in a semiconductor substrate. It also comprises a strip of floating gate, a strip of dielectric and a strip of barrier polysilicon, each of these strips being provided with a respective pair of small lateral fins. The UPROM cell lastly comprises a control gate superimposed over and self-aligned with the floating gate.