Abstract: A computer-implemented method for the storage or transmission of a representation of genome sequencing data in a genomic file format including annotation data associated with the genome sequencing data, the genome sequencing data including reads of sequences of nucleotides, the method including the steps of: aligning the reads to one or more reference sequences thereby creating aligned reads, classifying the aligned reads according to classification rules based on mapping of the aligned reads on the one or more reference sequences, thereby creating classes of aligned reads, entropy encoding the classified aligned reads as a multiplicity of blocks of descriptors, structuring the blocks of descriptors with header information thereby creating Access Units of a first sort containing genome sequencing data, the method further including encoding annotation data into different Access Units of a second sort and indexing data into a master annotation index.

Abstract: An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupled to external memory and to the on-chip communication network. The memory interface supports accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network. A portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon.

Abstract: An integrated circuit an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. The receiver node is adapted to send flow control messages to the transmitter node. The flow control messages include credits that identify hardware resources of the receiver node that are available for receiving messages over the given logical channel. The transmitter node is adapted to maintain a running total of the credits included as part of the flow control messages communicated from the receiver node and to initiate transmission of messages to the receiver node in accordance with the running total of credits maintained at the transmitter node.

Abstract: A system-on-chip integrated circuit (and multi-chip systems based thereon) that includes a bridge interface that provides transparent bridging of data communicated between integrated circuits.

Abstract: An integrated circuit having an array of programmable processing elements linked by an on-chip communication network. Each processing element includes a plurality of processing cores, a local memory, and thread scheduling means for scheduling execution of threads on the processing cores of the given processing element. The thread scheduling means assigns threads to the processing cores of the given processing element in a configurable manner. The configuration of the thread scheduling means defines one or more logical symmetric multiprocessors for executing threads on the given processing element. A logical symmetric multiprocessor is realized by a defined set of processing cores assigned to a group of threads executing on the given processing element.