Abstract: Apparatus and methods for extending functionality of memory controllers in a processor-based device are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit that is communicatively coupled to a memory controller and a memory device. The memory access intercept circuit is configured to receive a memory write request that is directed to and received by the memory controller, and generates a write transaction identifier (ID) for the memory write request. The memory access intercept circuit then generates proxy write data containing the write transaction ID, and sends the proxy write data to the memory controller. The memory access intercept circuit subsequently intercepts the actual write data directed to the memory controller, and stores the write data in a write data buffer in association with the write transaction ID.

Abstract: A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.

Abstract: A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.

Abstract: Apparatus and methods for extending functionality of memory controllers in a processor-based device are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit that is communicatively coupled to a memory controller and a memory device. The memory access intercept circuit is configured to receive a memory write request that is directed to and received by the memory controller, and generates a write transaction identifier (ID) for the memory write request. The memory access intercept circuit then generates proxy write data containing the write transaction ID, and sends the proxy write data to the memory controller. The memory access intercept circuit subsequently intercepts the actual write data directed to the memory controller, and stores the write data in a write data buffer in association with the write transaction ID.

Abstract: A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.

Abstract: A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.

Abstract: System address reconstruction logic in accordance with one embodiment of the present description, reconstructs a system address from a channel address translated from the system address. The system address reconstruction logic includes logic configured to reconstruct one or more systems address fields as a function of the channel address, the number of memory controller target ways of the memory being equal to three, the number of bits of the granularity of interleaving of data among the memory controller target ways, the number of channels per memory controller target way, and the number of bits of the granularity of interleaving of data among the channels of a memory controller target way. Other aspects are described herein.

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

Abstract: Electronic circuitry of a computing system is described where the computing system includes a multi-level system memory where the multi-level system memory includes a near memory cache. The computing system directs system memory access requests whose addresses map to a same near memory cache slot to a same home caching agent so that the same home caching agent can characterize individual cache lines as inclusive or non-inclusive before forwarding the requests to a system memory controller, and where the computing system directs other system memory access requests to the system memory controller without passing the other requests through a home caching agent. The electronic circuitry is to modify the respective original addresses of the other requests to include a special code that causes the other system memory access requests to map to a specific pre-determined set of slots within the near memory cache.

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

Abstract: Electronic circuitry of a computing system is described where the computing system includes a multi-level system memory where the multi-level system memory includes a near memory cache. The computing system directs system memory access requests whose addresses map to a same near memory cache slot to a same home caching agent so that the same home caching agent can characterize individual cache lines as inclusive or non-inclusive before forwarding the requests to a system memory controller, and where the computing system directs other system memory access requests to the system memory controller without passing the other requests through a home caching agent. The electronic circuitry is to modify the respective original addresses of the other requests to include a special code that causes the other system memory access requests to map to a specific pre-determined set of slots within the near memory cache.

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

Abstract: Methods and apparatus related to efficient implementation of geometric series are discussed herein. For example, memory stores data corresponding to a geometric series. Logic, coupled to the memory, generates a channel address based at least in part on a summation of a tag address and one or more geometric series components of the geometric series. Other embodiments are also claimed.

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

Abstract: System address reconstruction logic in accordance with one embodiment of the present description, reconstructs a system address from a channel address translated from the system address. The system address reconstruction logic includes logic configured to reconstruct one or more systems address fields as a function of the channel address, the number of memory controller target ways of the memory being equal to three, the number of bits of the granularity of interleaving of data among the memory controller target ways, the number of channels per memory controller target way, and the number of bits of the granularity of interleaving of data among the channels of a memory controller target way. Other aspects are described herein.

Abstract: A reordering command queue for reordering memory accesses in a computer system. The reordering command queue may reduce the power that is typically used up in computer systems when performing accesses to main memory by improving the scheduling of memory accesses with a pattern that is optimized for power and which has no (or negligible) impacting on performance. During a compare operation, the address corresponding to the command stored in each of one or more current storage locations of the reordering command queue may be compared to the address corresponding to the command stored in an adjacent storage location to determine whether the commands are in a desired order. In response to one or more of the commands not being in the desired order, a reordering operation may be performed, which may reorder each of the one or more commands from a current storage location to the adjacent storage location.

Abstract: In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

Abstract: A method for minimizing noise in an integrated circuit is described, the method including choosing a net to be analyzed, determining that the total path length of conductive paths coupled to a driver within the net exceed a maximum acceptable length for that given driver according to the minimum acceptable noise levels for that given net, and inserting at least one buffer within the net at a position which is within the maximum acceptable length for conductive paths coupled to the driver.

Abstract: In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.