Abstract: Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.

Abstract: Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.

Abstract: During the formation of a metal line in a low-k dielectric material, an upper portion of a trench formed in a capping layer and the low-k dielectric material is treated to provide enlarged tapering or corner rounding, thereby significantly improving the fill capabilities of subsequent metal deposition processes. In one particular embodiment, an additional etch process is performed after etching through the capping layer and the low-k dielectric layer and after resist removal.

Abstract: In an etch process for forming via openings and trench openings in a low-k dielectric layer, the material removal of an underlying etch stop layer is decoupled from the etching through the low-k dielectric in that the reduction in thickness is substantially achieved during the resist removal. For this purpose, the resist plasma etch may correspondingly be controlled to obtain the desired target thickness of the etch stop layer, wherein fluorine may be provided from an external source and/or fluorine may be generated in a controlled manner from polymer layers deposited within the etch chamber.

Abstract: By providing a contact etch stop layer, the stress in channel regions of different transistor types may be effectively controlled, wherein tensile and compressive stress portions of the contact etch stop layer may be obtained by well-established processes, such as wet chemical etch, plasma etch, ion implantation, plasma treatment and the like. Hence, a significant improvement in transistor performance may be obtained while not significantly contributing to process complexity.

Abstract: During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced by the contact etch step layer rather than by a combination of the spacer elements and the etch stop layer, thereby significantly facilitating the stress engineering in the channel region. By additionally performing a plasma treatment, different amounts of stress may be created in different transistor devices without unduly contributing to process complexity.

Abstract: By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the probability of wafer arcing. Subsequently, the delineation trench or open area may be etched down to the respective etch stop layer in a further common etch process, during which a trench is formed above the via opening.

Abstract: A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.

Abstract: By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the probability of wafer arcing. Subsequently, the delineation trench or open area may be etched down to the respective etch stop layer in a further common etch process, during which a trench is formed above the via opening.

Abstract: The anisotropic etch process for forming circuit elements such as a gate electrode is accomplished by using a hard mask instead of a resist feature, thereby avoiding a complex resist trim process when critical dimensions are required, which are well below the resolution of the involved photolithography. Moreover, the critical dimension may be adjusted by means of a deposition process rather than by a resist trim process.

Abstract: The present invention is directed to a semiconductor device having a gate electrode includes of a plurality of sidewalls, each having a recess formed therein. The present invention is also directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of dopant material in a layer of polysilicon and etching the layer of polysilicon to define a gate electrode having a plurality of sidewalls, each of which have a recess formed therein.

Abstract: In an etch process for forming via openings and trench openings in a low-k dielectric layer, the material removal of an underlying etch stop layer is decoupled from the etching through the low-k dielectric in that the reduction in thickness is substantially achieved during the resist removal. For this purpose, the resist plasma etch may correspondingly be controlled to obtain the desired target thickness of the etch stop layer, wherein fluorine may be provided from an external source and/or fluorine may be generated in a controlled manner from polymer layers deposited within the etch chamber.

Abstract: During the formation of a metal line in a low-k dielectric material, an upper portion of a trench formed in a capping layer and the low-k dielectric material is treated to provide enlarged tapering or corner rounding, thereby significantly improving the fill capabilities of subsequent metal deposition processes. In one particular embodiment, an additional etch process is performed after etching through the capping layer and the low-k dielectric layer and after resist removal.

Abstract: A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.

Abstract: By providing a contact etch stop layer, the stress in channel regions of different transistor types may be effectively controlled, wherein tensile and compressive stress portions of the contact etch stop layer may be obtained by well-established processes, such as wet chemical etch, plasma etch, ion implantation, plasma treatment and the like. Hence, a significant improvement in transistor performance may be obtained while not significantly contributing to process complexity.

Abstract: During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced by the contact etch step layer rather than by a combination of the spacer elements and the etch stop layer, thereby significantly facilitating the stress engineering in the channel region. By additionally performing a plasma treatment, different amounts of stress may be created in different transistor devices without unduly contributing to process complexity.

Abstract: For patterning an opening through a patterned material, a coating material, a slow-etch material, and a photoresist material are deposited over the patterned material. The opening is patterned through the photoresist material, and the slow-etch material exposed through the opening is etched away. The photoresist material and the coating material exposed through the opening are then etched away. A remaining portion of the slow-etch hard-mask material and the patterned material exposed through the opening are then etched away such that the coating material outside of the opening is exposed. A remaining portion of the coating material is then etched away with an etch agent that does not etch the patterned material.

Abstract: The anisotropic etch process for forming circuit elements such as a gate electrode is accomplished by using a hard mask instead of a resist feature, thereby avoiding a complex resist trim process when critical dimensions are required, which are well below the resolution of the involved photolithography. Moreover, the critical dimension may be adjusted by means of a deposition process rather than by a resist trim process.

Abstract: The effect of resist poisoning may be eliminated or at least substantially reduced in the formation of a low-k metallization layer, in that a nitrogen-containing barrier/etch stop layer is provided with a significantly reduced nitrogen concentration at an interface in contact with said low-k dielectric material. Consequently, diffusion of nitrogen and nitrogen compounds in vias formed in said low-k dielectric layer is significantly suppressed, so that in a subsequent photolithographic step, interaction of nitrogen and nitrogen compounds with the photoresist is remarkably reduced.

Abstract: A method for forming an integrated circuit includes etching a first opening to a first depth in a dielectric material over a semiconductor device on a first semiconductor substrate and etching a second opening to a second depth in the dielectric material over the first semiconductor substrate. The first and second openings are differently sized to respectively etch to the first and second depths in about the same time due to etch lag. The first and second openings are filled with conductive material.