Abstract: Provided is a test apparatus that tests a device under test, comprising a control apparatus that controls the test apparatus; a pattern generator that generates a plurality of test patterns to be provided to a plurality of input terminals of the device under test; a plurality of variable delay circuits that designate a timing for supplying each of the plurality of test patterns to a corresponding input terminal of the plurality of input terminals; and a plurality of micro-controllers that operate in parallel, according to instructions from the control apparatus, to each measure a delay amount of a variable delay circuit when the variable delay circuit is set with a prescribed delay setting value and store the delay setting value in association with the measured delay amount.

Abstract: Provided is a test apparatus that tests a device under test, comprising a control apparatus that controls the test apparatus; a pattern generator that generates a plurality of test patterns to be provided to a plurality of input terminals of the device under test; a plurality of variable delay circuits that designate a timing for supplying each of the plurality of test patterns to a corresponding input terminal of the plurality of input terminals; and a plurality of micro-controllers that operate in parallel, according to instructions from the control apparatus, to each measure a delay amount of a variable delay circuit when the variable delay circuit is set with a prescribed delay setting value and store the delay setting value in association with the measured delay amount.

Abstract: There is provided a testing apparatus including: a pattern generator that generates an address signal and a data signal to be supplied to a plurality of memories under test and an expectation signal; a plurality of logic comparators that generate fail data when an output signal output from the plurality of memories under test and the expectation signal are not identical with each other; a plurality of fail memories that store the fail data generated from the plurality of logic comparators; a plurality of memory controllers that generate bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories; a plurality of universal buffer memories that store the bad address information generated from the plurality of memory controllers; and a plurality of bad information writing sections that concurrently write bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the

Abstract: There is provided a testing apparatus including: a pattern generator that generates an address signal and a data signal to be supplied to a plurality of memories under test and an expectation signal; a plurality of logic comparators that generate fail data when an output signal output from the plurality of memories under test and the expectation signal are not identical with each other; a plurality of fail memories that store the fail data generated from the plurality of logic comparators; a plurality of memory controllers that generate bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories; a plurality of universal buffer memories that store the bad address information generated from the plurality of memory controllers; and a plurality of bad information writing sections that concurrently write bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the

Abstract: There is provided a memory testing apparatus which can complete a DC test FOR a memory in a short time period.

Abstract: A fine variable delay circuit includes a buffer having an input connected to a signal input terminal and an output. The buffer has an output impedance and outputs a logical level from the output. The fine variable delay circuit also includes a schmidt trigger buffer having an input connected to the output of the buffer and an output connected to a signal output terminal, a CMOS transistor having a gate and two electrodes, the gate being connected to a connection point between said buffer and said schmidt trigger buffer.

Abstract: First and second exclusive-OR gates (hereinafter referred to as EXOR gates) are provided, which are both connected at one input side to a delay input terminal. The other input side of the first EXOR gate is grounded and the other input side of the second EXOR gate is connected to a select signal input terminal. A capacitor is connected between the output side of the first EXOR gate and the output side of the second EXOR gate. The output side of the first EXOR gate is connected to a delay output terminal by way of a buffer which outputs logical levels. The buffer has a threshold value and outputs one or the other binary logical level depending on whether the input thereto is above or below a threshold value.