Patents by Inventor Masumi Kasahara
Masumi Kasahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8686885Abstract: A semiconductor integrated circuit device having A/D converters for converting, by means of digital correction processing, analog input signals into digital signals is reduced in area. The semiconductor integrated circuit device has a first A/D converter and a second A/D converter. In a first mode, a first test signal is inputted to both the first and second A/D converters, and a first correction coefficient for the first A/D converter and a second correction coefficient for the second A/D converter are calculated. In a second mode, the first A/D converter converts a first analog signal into a first digital signal by subjecting the first analog signal to a first digital correction processing and the second A/D converter converts a second analog signal into a second digital signal by subjecting the second analog signal to a second digital correction processing.Type: GrantFiled: January 17, 2013Date of Patent: April 1, 2014Assignee: Renesas Electronics CorporationInventors: Tatsuji Matsuura, Hideo Nakane, Masumi Kasahara, Ryuichi Ujiie, Keisuke Kimura, Oshima Takashi
-
Publication number: 20130249720Abstract: A semiconductor integrated circuit device having A/D converters for converting, by means of digital correction processing, analog input signals into digital signals is reduced in area. The semiconductor integrated circuit device has a first A/D converter and a second A/D converter. In a first mode, a first test signal is inputted to both the first and second A/D converters, and a first correction coefficient for the first A/D converter and a second correction coefficient for the second A/D converter are calculated. In a second mode, the first A/D converter converts a first analog signal into a first digital signal by subjecting the first analog signal to a first digital correction processing and the second A/D converter converts a second analog signal into a second digital signal by subjecting the second analog signal to a second digital correction processing.Type: ApplicationFiled: January 17, 2013Publication date: September 26, 2013Applicant: Renesas Electronics CorporationInventors: Tatsuji Matsuura, Hideo Nakane, Masumi Kasahara, Ryuichi Ujiie, Keisuke Kimura, Oshima Takashi
-
Patent number: 8107912Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: GrantFiled: December 22, 2010Date of Patent: January 31, 2012Assignees: Renesas Electronics Corporation, Tipcom LimitedInventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
-
Publication number: 20110092175Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: ApplicationFiled: December 22, 2010Publication date: April 21, 2011Applicants: RENESAS TECHNOLOGY CORP., TTPCOM LIMITEDInventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
-
Patent number: 7885626Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: GrantFiled: March 27, 2008Date of Patent: February 8, 2011Assignees: Renesas Technology Corp., TTPCOM LimitedInventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
-
Patent number: 7800452Abstract: The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.Type: GrantFiled: October 24, 2007Date of Patent: September 21, 2010Assignee: Renesas Electronics CorporationInventors: Manabu Kawabe, Kazuyuki Hori, Satoshi Tanaka, Yukinori Akamine, Masumi Kasahara, Kazuo Watanabe
-
Patent number: 7583215Abstract: The A/D converter converting an analog input signal into a digital output signal is constructed with a band pass ?? modulator. The band pass ?? modulator includes: a resonator showing a band-pass characteristic at a predetermined frequency and an attenuation characteristic at another frequency; a quantizer; and a local D/A converter. A signal of difference between the analog input signal and a local analog signal of the local D/A converter is supplied to the resonator. The A/D converter further includes an adder for supplying the analog input signal to an input of the quantizer. In addition, signal transmission circuits for reducing the influence of spike noise of the quantizer on the input to the resonator are connected between an input of the adder and an input of resonator selectively. The A/D converter constructed with the band pass ?? modulator is improved in S/N ratio.Type: GrantFiled: January 14, 2008Date of Patent: September 1, 2009Assignee: Renesas Technology Corp.Inventors: Takaya Yamamoto, Tatsuji Matsuura, Masumi Kasahara, Hideo Nakane, Junya Kudo, Yoshitaka Jingu
-
Patent number: 7515648Abstract: A transmitter that can reduce noise without using an SAW filter whose IC integration is hard, and copes with two modulation formats of constant envelope modulation and non-constant envelope modulation, and a downsized and low-cost wireless communication apparatus that uses the transmitter are provided. The transmitter includes a quadrature modulator that modulates an input signal by quadrature modulation, a first amplifier that amplifies a modulation signal outputted by the quadrature modulator, and a second amplifier that amplifies an output signal of the first amplifier. The first amplifier operates as a limiter when the modulation format is the constant envelope modulation, and performs linear operation when the modulation format is the non-constant envelope modulation.Type: GrantFiled: December 21, 2004Date of Patent: April 7, 2009Assignee: Renesas Technology Corp.Inventors: Taizo Yamawaki, Masahiro Ito, Masumi Kasahara, Hiroaki Matsui
-
Patent number: 7504903Abstract: In a communication semiconductor integrated circuit device, an oscillator of a PLL circuit can operate in a plurality of frequency bands. With a control voltage (Vc) of the oscillator fixed to a predetermined value (VDC), an oscillation frequency of the oscillator is measured for each band to be stored in a storage. When the PLL operates, a setting value to specify a band is compared with the measured frequency values stored in the storage. As a result of the comparison, a band to be actually used by the oscillator is determined.Type: GrantFiled: November 6, 2006Date of Patent: March 17, 2009Assignees: Renesas Technology Corp., TTPCom LimitedInventors: Masumi Kasahara, Hirotaka Osawa, Robert Astle Henshaw
-
Patent number: 7426377Abstract: A ?? transmitter that permits setting of a loop filter LF, a charge pump current and other factors to the same conditions even if it is operated in a plurality of frequency bands, therefore allows the number of components to be reduced and at the same time enables the angle between the phases of local signals for reception use to be close to exactly 90°, which is a feature ensuring robustness against inter-element variations and accordingly suitable for large scale integration, is to be provided. The oscillation frequency of a VCO is set to an even-number multiple of the transmit frequency, and generates transmit signals via a divider. A device that varies the gain according to the amplitude component of modulating signals is added to an amplifier whose input is signals from the VCO, and the transmission of modulating signals involving amplitude modulation, such as EDGE, is thereby made possible.Type: GrantFiled: August 19, 2005Date of Patent: September 16, 2008Assignee: Renesas Technology Corp.Inventors: Satoshi Tanaka, Kazuyuki Hori, Manabu Kawabe, Yukinori Akamine, Masumi Kasahara, Kazuo Watanabe
-
Patent number: 7414821Abstract: Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.Type: GrantFiled: September 18, 2007Date of Patent: August 19, 2008Assignee: Renesas Technology Corp.Inventors: Kumiko Takikawa, Satoshi Tanaka, Masumi Kasahara
-
Publication number: 20080182538Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: ApplicationFiled: March 27, 2008Publication date: July 31, 2008Inventors: Satoshi TANAKA, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
-
Publication number: 20080169953Abstract: The A/D converter converting an analog input signal into a digital output signal is constructed with a band pass ?? modulator. The band pass ?? modulator includes: a resonator showing a band-pass characteristic at a predetermined frequency and an attenuation characteristic at another frequency; a quantizer; and a local D/A converter. A signal of difference between the analog input signal and a local analog signal of the local D/A converter is supplied to the resonator. The A/D converter further includes an adder for supplying the analog input signal to an input of the quantizer. In addition, signal transmission circuits for reducing the influence of spike noise of the quantizer on the input to the resonator are connected between an input of the adder and an input of resonator selectively. The A/D converter constructed with the band pass ?? modulator is improved in S/N ratio.Type: ApplicationFiled: January 14, 2008Publication date: July 17, 2008Inventors: Takaya YAMAMOTO, Tatsuji Matsuura, Masumi Kasahara, Hideo Nakane, Junya Kudo, Yoshitaka Jingu
-
Patent number: 7366489Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: GrantFiled: December 23, 2003Date of Patent: April 29, 2008Assignees: TTPCOM Limited, Renesas Technology Corp.Inventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
-
Publication number: 20080061890Abstract: The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.Type: ApplicationFiled: October 24, 2007Publication date: March 13, 2008Inventors: Manabu Kawabe, Kazuyuki Hori, Satoshi Tanaka, Yukinori Akamine, Masumi Kasahara, Kazuo Watanabe
-
Publication number: 20080030911Abstract: Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.Type: ApplicationFiled: September 18, 2007Publication date: February 7, 2008Inventors: Kumiko Takikawa, Satoshi Tanaka, Masumi Kasahara
-
Patent number: 7313369Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit forming part of the transmission PLL circuit is configured to be operable in a plurality of bands. A circuit for measuring the oscillating frequency of the oscillator circuit forming part of the transmission PLL circuit is also used for measuring the oscillating frequency of the oscillator circuit forming part of the reception PLL circuit or for measuring the oscillating frequency of the oscillator circuit for the intermediate frequency.Type: GrantFiled: May 5, 2005Date of Patent: December 25, 2007Assignees: Renesas Technology Corp., TTPcom LimitedInventors: Hirotaka Oosawa, Jiro Shinbo, Noriyuki Kurakami, Masumi Kasahara, Robert Astle Henshaw
-
Publication number: 20070281651Abstract: The invention provides a communication semiconductor integrated circuit device (RF IC) capable of pulling in the frequency of a PLL circuit to a desired set frequency at high speed even in the case where a frequency settable range of the PLL circuit is wide without providing a current source other than a current source for charging and discharging in an normal operation. An oscillator as a component of a PLL circuit is constructed so as to be operative in a plurality of bands. In a state where a control voltage of the oscillator is fixed to a predetermined value, an oscillation frequency of the oscillator is measured in each of bands and stored in a storing circuit. A set value for designating a band supplied at the time of PLL operation is compared with the stored measured frequency value. From a result of comparison, a band to be actually used in the oscillator is determined, and a frequency difference between the maximum frequency of the selected band and the set frequency is obtained.Type: ApplicationFiled: June 8, 2007Publication date: December 6, 2007Inventors: Hirotaka Oosawa, Masumi Kasahara, Noriyuki Kurakami, Toshiya Uozumi
-
Patent number: 7301405Abstract: The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.Type: GrantFiled: August 12, 2005Date of Patent: November 27, 2007Assignee: Renesas Technology Corp.Inventors: Manabu Kawabe, Kazuyuki Hori, Satoshi Tanaka, Yukinori Akamine, Masumi Kasahara, Kazuo Watanabe
-
Patent number: 7298600Abstract: Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.Type: GrantFiled: April 13, 2005Date of Patent: November 20, 2007Assignee: Renesas Technology Corp.Inventors: Kumiko Takikawa, Satoshi Tanaka, Masumi Kasahara