Patents by Inventor Masuo Koga
Masuo Koga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10770371Abstract: A base plate (1) made of a metal has a through-hole (2). An insulating substrate (3) is provided on the base plate (1). A semiconductor chip (4) is provided on the insulating substrate (3). A case (8) has a screw-hole (9) communicating with the through-hole (2), covers the insulating substrate (3) and the semiconductor chip (4), and is disposed on the base plate (1). A screw (11) made of a metal is inserted into the through-hole (2) and the screw-hole (9) to fix the case (8) to the base plate (1). A flexible material (12) having flexibility is filled in a cavity between a bottom surface of the screw-hole (9) in the case (8) and a distal end of the screw (11).Type: GrantFiled: July 9, 2014Date of Patent: September 8, 2020Assignee: Mitsubishi Electric CorporationInventors: Yoichi Hironaka, Masuo Koga
-
Publication number: 20170170096Abstract: A base plate (1) made of a metal has a through-hole (2). An insulating substrate (3) is provided on the base plate (1). A semiconductor chip (4) is provided on the insulating substrate (3). A case (8) has a screw-hole (9) communicating with the through-hole (2), covers the insulating substrate (3) and the semiconductor chip (4), and is disposed on the base plate (1). A screw (11) made of a metal is inserted into the through-hole (2) and the screw-hole (9) to fix the case (8) to the base plate (1). A flexible material (12) having flexibility is filled in a cavity between a bottom surface of the screw-hole (9) in the case (8) and a distal end of the screw (11).Type: ApplicationFiled: July 9, 2014Publication date: June 15, 2017Applicant: Mitsubishi Electric CorporationInventors: Yoichi HIRONAKA, Masuo KOGA
-
Patent number: 9257408Abstract: A soldering portion (4) and a Ni plating mark (5) are simultaneously forming by plating on a wiring pattern (2) of an insulating substrate (1). A semiconductor chip (6) is mounted on the insulating substrate (1). A position of the insulating substrate (1) is recognized by the Ni plating mark (5) and a wire (7) is bonded to the semiconductor chip (6). An electrode (8) is joined to the soldering portion (4) by solder (9). The insulating substrate (1), the semiconductor chip (6), the wire (7), and the electrode (8) are encapsulated in an encapsulation material (13).Type: GrantFiled: November 21, 2012Date of Patent: February 9, 2016Assignee: Mitsubishi Electric CorporationInventors: Takayuki Matsumoto, Hirotaka Onishi, Masuo Koga
-
Publication number: 20150262962Abstract: A soldering portion (4) and a Ni plating mark (5) are simultaneously forming by plating on a wiring pattern (2) of an insulating substrate (1). A semiconductor chip (6) is mounted on the insulating substrate (1). A position of the insulating substrate (1) is recognized by the Ni plating mark (5) and a wire (7) is bonded to the semiconductor chip (6). An electrode (8) is joined to the soldering portion (4) by solder (9). The insulating substrate (1), the semiconductor chip (6), the wire (7), and the electrode (8) are encapsulated in an encapsulation material (13).Type: ApplicationFiled: November 21, 2012Publication date: September 17, 2015Applicant: Mitsubishi Electric CorporationInventors: Takayuki Matsumoto, Hirotaka Onishi, Masuo Koga
-
Patent number: 8569890Abstract: A power semiconductor device module includes: a base plate; an insulating substrate mounted on the base plate; and a diode chip mounted on the insulating substrate, wherein the insulating substrate has an upper surface electrode layer disposed on an upper main surface and a lower surface electrode layer disposed on a lower main surface, the diode chip is joined onto the upper surface electrode layer, the lower surface electrode layer is joined onto the upper main surface of the base plate, and a thermal resistance reducing section that reduces thermal resistance is provided in lower surface electrode layer or the base plate of a portion corresponding to a place immediately below the diode chip.Type: GrantFiled: June 25, 2012Date of Patent: October 29, 2013Assignee: Mitsubishi Electric CorporationInventors: Kazuhiro Morishita, Masuo Koga, Yukimasa Hayashida
-
Publication number: 20130249100Abstract: A power semiconductor device module includes: a base plate; an insulating substrate mounted on the base plate; and a diode chip mounted on the insulating substrate, wherein the insulating substrate has an upper surface electrode layer disposed on an upper main surface and a lower surface electrode layer disposed on a lower main surface, the diode chip is joined onto the upper surface electrode layer, the lower surface electrode layer is joined onto the upper main surface of the base plate, and a thermal resistance reducing section that reduces thermal resistance is provided in lower surface electrode layer or the base plate of a portion corresponding to a place immediately below the diode chip.Type: ApplicationFiled: June 25, 2012Publication date: September 26, 2013Applicant: Mitsubishi Electric CorporationInventors: Kazuhiro MORISHITA, Masuo KOGA, Yukimasa HAYASHIDA
-
Patent number: 8466551Abstract: A semiconductor device includes a main current external electrode for connecting a high-voltage main current electrode of a power semiconductor element to the outside, and a resin case into which the main current external electrode is press fitted. The main current external electrode has a press-fitted fixing portion and a claw fixing portion for fixation to the resin case. The claw fixing portion includes a projection passing through a through hole defined in the resin case, and having a bendable claw portion at its tip end.Type: GrantFiled: July 21, 2011Date of Patent: June 18, 2013Assignee: Mitsubishi Electric CorporationInventor: Masuo Koga
-
Publication number: 20120119369Abstract: A semiconductor device includes a main current external electrode for connecting a high-voltage main current electrode of a power semiconductor element to the outside, and a resin case into which the main current external electrode is press fitted. The main current external electrode has a press-fitted fixing portion and a claw fixing portion for fixation to the resin case. The claw fixing portion includes a projection passing through a through hole defined in the resin case, and having a bendable claw portion at its tip end.Type: ApplicationFiled: July 21, 2011Publication date: May 17, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Masuo Koga
-
Patent number: 7554192Abstract: A semiconductor device that includes an insulating substrate having an upper conductor formed on an upper surface thereof and a lower conductor formed on a lower surface of the insulating substrate. The device also includes a semiconductor element mounted on the upper surface of the insulating substrate with an under-element solder therebetween. The device further includes a heat sink whereon the insulating substrate is mounted with an under-substrate solder therebetween. The device additionally includes a silicone gel covering the semiconductor element, the under-element solder, and the upper conductor. In addition, the device includes a filler covering the lower conductor and the under-substrate solder, without covering the semiconductor element, the under-element solder, and the upper conductor, and having a thermal conductivity larger than a thermal conductivity of air and a fluidity higher than a fluidity of the silicone gel.Type: GrantFiled: October 26, 2006Date of Patent: June 30, 2009Assignee: Mitsubishi Electric CorporationInventors: Masuo Koga, Tetsuo Mizoshiri, Yukimasa Hayashida
-
Patent number: 7405448Abstract: A first insulating substrate is formed on a heat sink, and a semiconductor element is formed thereon. An insulating resin casing is formed so as to cover the first insulating substrate and the semiconductor element. A second insulating substrate is mounted inside the insulating resin casing apart from the first insulating substrate. On the second insulating substrate, a resistance element that functions as a gate balance resistance is fixed by soldering. The second insulating substrate on which the resistance element was thus mounted was made apart from the first insulating substrate on which the semiconductor element was mounted, and was mounted on the side of the insulating resin casing.Type: GrantFiled: October 3, 2006Date of Patent: July 29, 2008Assignee: Mitsubishi Electric CorporationInventors: Masuo Koga, Tetsuo Mizoshiri, Yukimasa Hayashida
-
Publication number: 20080006932Abstract: A semiconductor device according to the present invention has an insulating substrate having an upper conductor formed on the upper surface and a lower conductor formed on the lower surface; a semiconductor element mounted on the insulating substrate with an under-element solder therebetween; a heat sink whereon the insulating substrate is mounted with an under-substrate solder therebetween; a silicone gel covering the semiconductor element, the under-element solder and the upper conductor; and a filler covering the lower conductor and the under-substrate solder, and having a thermal conductivity larger than the thermal conductivity of air and a fluidity higher than the fluidity of the silicone gel.Type: ApplicationFiled: October 26, 2006Publication date: January 10, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Masuo KOGA, Tetsuo Mizoshiri, Yukimasa Hayashida
-
Publication number: 20070284745Abstract: A first insulating substrate is formed on a heat sink, and a semiconductor element is formed thereon. An insulating resin casing is formed so as to cover the first insulating substrate and the semiconductor element. A second insulating substrate is mounted inside the insulating resin casing apart from the first insulating substrate. On the second insulating substrate, a resistance element that functions as a gate balance resistance is fixed by soldering. The second insulating substrate on which the resistance element was thus mounted was made apart from the first insulating substrate on which the semiconductor element was mounted, and was mounted on the side of the insulating resin casing.Type: ApplicationFiled: October 3, 2006Publication date: December 13, 2007Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Masuo KOGA, Tetsuo Mizoshiri, Yukimasa Hayashida
-
Patent number: 6900986Abstract: A power module includes a first substrate with a power semiconductor device mounted thereon, a second substrate with a control circuit for controlling the power semiconductor device formed thereon, a smoothing capacitor electrically connected to the power semiconductor device for smoothing a voltage to be externally supplied to the power semiconductor device, and a case including a case frame and a case lid. The case has an interior in which the first substrate, the second substrate and the smoothing capacitor are disposed, and the smoothing capacitor is disposed in contact with a side surface of the case frame.Type: GrantFiled: March 29, 2004Date of Patent: May 31, 2005Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Nobuyoshi Kimoto, Takanobu Yoshida, Naoki Yoshimatsu, Masuo Koga, Dai Nakajima, Gourab Majumdar, Masakazu Fukada
-
Publication number: 20040179341Abstract: A power module includes a box-shaped smoothing capacitor (20) for smoothing a DC supply voltage to be externally applied to a power semiconductor device (5). The smoothing capacitor (20) is in contact with a side surface of a case frame (6) including a side (along which an N-terminal (8N) and a P-terminal (8P) are arranged) of a top surface of the case frame (6), and has a top surface level with the top surface of the case frame (6). An N-electrode (21N) and a P-electrode (21P) of the smoothing capacitor (20) are disposed on the top surface of the smoothing capacitor (20) and in proximity to the N-terminal (8N) and the P-terminal (8P) of a power module body portion (99), respectively. The power module can reduce a circuit inductance, is reduced in size and weight, and has good resistance to vibration.Type: ApplicationFiled: March 29, 2004Publication date: September 16, 2004Applicants: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corp.Inventors: Nobuyoshi Kimoto, Takanobu Yoshida, Naoki Yoshimatsu, Masuo Koga, Dai Nakajima, Gourab Majumdar, Masakazu Fukada
-
Patent number: 6762937Abstract: A power module includes a substrate with a power semiconductor device mounted thereon, a case having an interior in which the substrate is disposed, a cooling fin having a surface on which the substrate and the case are placed, and a smoothing capacitor disposed on an opposite surface of the cooling fin from the surface on which the substrate is placed, the smoothing capacitor being electrically connected to the power semiconductor device for smoothing a voltage to be externally supplied to the power semiconductor device.Type: GrantFiled: December 10, 2002Date of Patent: July 13, 2004Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Nobuyoshi Kimoto, Takanobu Yoshida, Naoki Yoshimatsu, Masuo Koga, Dai Nakajima, Gourab Majumdar, Masakazu Fukada
-
Patent number: 6700073Abstract: A silicone resin for sealing a semiconductor chip. A cured silicone resin, which is obtained by curing the silicone resin at a given temperature, has a percent elongation, after fracture, measured at a room temperature, not less than 4% of a penetration number at room temperature. A semiconductor device sealed with the silicone resin, when subjected to a heat cycle or a vibration test, provides resistance to cracking, forming of voids, and interfacial peeling-off. The cured silicone resin may have a penetration number not less than 10 and not more than 80 and a loss elasticity not less than 17% of the storage elasticity. A resin member made of the cured silicone resin and sealing a semiconductor chip may include a filler, such as silica or alumina, having a coefficient of linear thermal expansion lower than that of the cured silicone resin.Type: GrantFiled: October 4, 2001Date of Patent: March 2, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Seiki Hiramatsu, Satoshi Yanaura, Masuo Koga, Hirofumi Fujioka
-
Publication number: 20030063442Abstract: A power module includes a box-shaped smoothing capacitor (20) for smoothing a DC supply voltage to be externally applied to a power semiconductor device (5). The smoothing capacitor (20) is in contact with a side surface of a case frame (6) including a side (along which an N-terminal (8N) and a P-terminal (8P) are arranged) of a top surface of the case frame (6), and has a top surface level with the top surface of the case frame (6). An N-electrode (21N) and a P-electrode (21P) of the smoothing capacitor (20) are disposed on the top surface of the smoothing capacitor (20) and in proximity to the N-terminal (8N) and the P-terminal (8P) of a power module body portion (99), respectively. The power module can reduce a circuit inductance, is reduced in size and weight, and has good resistance to vibration.Type: ApplicationFiled: December 10, 2002Publication date: April 3, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Nobuyoshi Kimoto, Takanobu Yoshida, Naoki Yoshimatsu, Masuo Koga, Dai Nakajima, Gourab Majumdar, Masakazu Fukada
-
Patent number: 6522544Abstract: A power module includes a box-shaped smoothing capacitor (20) for smoothing a DC supply voltage to be externally applied to a power semiconductor device (5). The smoothing capacitor (20) is in contact with a side surface of a case frame (6) including a side (along which an N-terminal (8N) and a P-terminal (8P) are arranged) of a top surface of the case frame (6), and has a top surface level with the top surface of the case frame (6). An N-electrode (21N) and a P-electrode (21P) of the smoothing capacitor (20) are disposed on the top surface of the smoothing capacitor (20) and in proximity to the N-terminal (8N) and the P-terminal (8P) of a power module body portion (99), respectively. The power module can reduce a circuit inductance, is reduced in size and weight, and has good resistance to vibration.Type: GrantFiled: October 17, 2000Date of Patent: February 18, 2003Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Nobuyoshi Kimoto, Takanobu Yoshida, Naoki Yoshimatsu, Masuo Koga, Dai Nakajima, Gourab Majumdar, Masakazu Fukada
-
Publication number: 20020070439Abstract: A silicone resin for sealing a semiconductor chip is disclosed. A cured silicone resin, which is obtained by curing the silicone resin at a given temperature, has a number of percent elongation after fracture measured at a room temperature not less than 4% of a penetration number at a room temperature. A semiconductor device sealed with the silicone resin, when applied to a heat cycle or a vibration test, provides resistances to cracking, voiding, or interfacial peeling-off. The cured silicone resin may have a penetration number not less than 10 and not more than 80 and a loss elasticity not less than 17% of the storage elasticity. A resin member made of the cured silicone resin and sealing a semiconductor chip may include a filler, such as silica or alumina, of which coefficient of linear thermal expansion is lower than that of the cured silicone resin.Type: ApplicationFiled: October 4, 2001Publication date: June 13, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Seiki Hiramatsu, Satoshi Yanaura, Masuo Koga, Hirofumi Fujioka
-
Patent number: 5864143Abstract: An ion implantation apparatus and process for ion implantation which eliminates the deterioration of device characteristics in the ion implantation process to a trench capacitor of a DRAM and increases the beam current without deteriorating the device characteristics.A high current ion implanter includes an implantation chamber, and arranged in the following order: a bias plate, a secondary electron implantation cylinder and an extension cylinder. The extension cylinder is adjacent to the implantation chamber, held to ground potential, and has a length of 10 to 25 cm..Type: GrantFiled: January 29, 1997Date of Patent: January 26, 1999Assignees: KTI Semiconductor Ltd., Texas Instruments IncorporatedInventors: Hirokazu Ueda, Masuo Koga, Shigeo Yasuda