Patents by Inventor Masuo Tsuji

Masuo Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6822164
    Abstract: A semiconductor device for supplying a signal to an electro-optical device which displays a two-dimensional image, includes first terminals which are formed along a first side of the semiconductor device in a longitudinal direction and have a length L1 in a direction intersecting the longitudinal direction at right angles; and second terminals which are formed along a second side intersecting the first side at right angles and have a length L2 which is greater than the length L1 in the longitudinal direction.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: November 23, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Masuo Tsuji, Masaaki Abe
  • Publication number: 20030151055
    Abstract: A semiconductor device for supplying a signal to an electro-optical device which displays a two-dimensional image, includes first terminals which are formed along a first side of the semiconductor device in a longitudinal direction and have a length L1 in a direction intersecting the longitudinal direction at right angles; and second terminals which are formed along a second side intersecting the first side at right angles and have a length L2 which is greater than the length L1 in the longitudinal direction.
    Type: Application
    Filed: January 21, 2003
    Publication date: August 14, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Masuo Tsuji, Masaaki Abe
  • Patent number: 5517041
    Abstract: Four gate electrodes of an n-type basic cell of a gate array are essentially oriented in a circular tangential direction of a radius relative to the center point Q of a cell. The electrodes have an upper and lower and a right and left symmetrical layout arrangement relative to the cell upper and lower center line and left and right center line. As a consequence, adjacent gate electrodes are positioned in a .+-.90.degree. rotating symmetry. Each gate electrode has wiring connection areas on both ends. The wiring connection areas overlap the pre-rotation wiring connection areas by a .+-.90.degree. rotation of the cell. Because the gate electrodes are essentially oriented along the circumference direction, the source and the drain are separated in the radial direction of the center of the cell. The wiring connection areas are not concentrated at the center of the cell, and this improves the wiring capabilities within the cell.
    Type: Grant
    Filed: June 25, 1993
    Date of Patent: May 14, 1996
    Assignee: Seiko Epson Corporation
    Inventors: Kensuke Torii, Yasuhiro Oguchi, Yasuhisa Hirabayashi, Masuo Tsuji
  • Patent number: 5450379
    Abstract: An information storage medium having both a read-only optical storage portion and a magnetic storage portion that can be written and read is provided. There is also disclosed a drive unit for use with this information storage medium. To control the optical head of this drive unit, a system controller and a CLV servomechanism are provided and form a control portion. When information is written or read to or from the magnetic storage portion, this control portion commands a disk-rotating mechanism to control the magnetic head of the drive unit based on information read from the optical storage portion of the medium. The magnetic storage portion can have either a single track or plural tracks. Interference between the optical head and the magnetic head can be avoided. The drive unit can adapt itself to the information storage medium having the optical storage portion of a large storage capacity and the magnetic storage portion that can be easily rewritten.
    Type: Grant
    Filed: August 12, 1993
    Date of Patent: September 12, 1995
    Assignee: Seiko Epson Corporation
    Inventors: Minoru Fujimori, Yasuhide Fujiwara, Satoshi Nebashi, Masuo Tsuji, Hiroaki Nomura, Noriyuki Kamijo, Tatsuya Shimoda
  • Patent number: 4392216
    Abstract: The integrated circuit, including MOS transistors, for driving the step motor of an analog display is substantially reduced in size by boosting the transistor gate voltage above the battery voltage applied to the source-drain terminals.
    Type: Grant
    Filed: December 24, 1980
    Date of Patent: July 5, 1983
    Assignee: Kabushiki Kaisha Suwa Seikosha
    Inventor: Masuo Tsuji
  • Patent number: 4122661
    Abstract: An electronic timepiece having detecting and control circuitry for preventing a digital display from being driven by a DC energizing signal is provided. The detecting and controlling circuitry is coupled intermediate the decoder circuitry and driving circuitry in an electronic timepiece digital display arrangement and detects the presence or absence of an intermediate frequency signal being produced by the timekeeping circuitry and applied to the driver circuitry to effect AC driving of the digital display. In response to detecting the absence of an intermediate frequency signal applied to the driver circuitry, the detecting and controlling circuit prevents the decoder circuitry from applying to the driver circuitry decoded timekeeping signals for effecting driving of the digital display, and thereby prevents inadvertent DC driving of the digital display.
    Type: Grant
    Filed: February 9, 1977
    Date of Patent: October 31, 1978
    Assignee: Kabushiki Kaisha Suwa Seikosha
    Inventor: Masuo Tsuji
  • Patent number: 3953963
    Abstract: An electronic digital display timepiece having a locking switch to prevent inadvertent correction of the timepiece, the locking switch being adapted to effect setting of at least one of the digits of time displayed. The electronic timepiece includes a quartz crystal oscillator circuit for producing high frequency time standard signals and a divider circuit including a plurality of divider stages adapted to produce low frequency timekeeping signals in response to said high frequency time standard signals. A display is associated with each of the plurality of divider stages in order to display digits of time in response to the low frequency timekeeping signals counted thereby. The count of certain of the divider stages may be corrected by correction switches provided a locking switch is first displaced from a locking mode to release mode.
    Type: Grant
    Filed: August 9, 1974
    Date of Patent: May 4, 1976
    Assignee: Kabushiki Kaisha Suwa Seikosha
    Inventors: Izuhiko Nishimura, Masuo Tsuji