Patents by Inventor Masuoka Fujio

Masuoka Fujio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6724035
    Abstract: A process for producing a semiconductor memory device comprises the steps of: (a) forming a floating gate on a semiconductor substrate having a dielectric film; (b) forming a side wall spacer comprising an insulating film on a side wall of the floating gate; (c) forming a groove by etching the semiconductor substrate using the side wall spacer as a mask; and (d) forming a low concentration impurity layer from one side wall to a bottom surface of the groove by an oblique ion implantation to the semiconductor substrate thus resulting, and forming a high concentration impurity layer from the other side wall to the bottom surface of the groove by in inverse oblique ion implantation.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: April 20, 2004
    Assignees: Sharp Kabushiki Kaisha
    Inventors: Masuoka Fujio, Takuji Tanigami, Yoshihisa Wada, Kenichi Tanaka, Hiroaki Shimizu
  • Publication number: 20020036316
    Abstract: A process for producing a semiconductor memory device comprises the steps of: (a) forming a floating gate on a semiconductor substrate having a dielectric film; (b) forming a side wall spacer comprising an insulating film on a side wall of the floating gate; (c) forming a groove by etching the semiconductor substrate using the side wall spacer as a mask; and (d) forming a low concentration impurity layer from one side wall to a bottom surface of the groove by an oblique ion implantation to the semiconductor substrate thus resulting, and forming a high concentration impurity layer from the other side wall to the bottom surface of the groove by in inverse oblique ion implantation.
    Type: Application
    Filed: December 11, 2000
    Publication date: March 28, 2002
    Inventors: Masuoka Fujio, Takuji Tanigami, Yoshihisa Wada, Kenichi Tanaka, Hiroaki Shimizu
  • Patent number: 5812453
    Abstract: Memory cells are divided into a plurality of series circuit units arranged in matrix fashion and comprising some memory cells connected in series. The memory cells each consist of non-volatile transistors provided with a control gate electrode, a floating gate electrode and an erase gate electrode. Bit lines to which one end of each of the series circuit units of the plurality of series circuit units arranged in one row are connected in common. Column lines are provided in common for the series circuit units that are arranged in one column and that are respectively connected to each control gate electrode of the memory cells constituting each of the series circuit unit. A voltage by which the selected non-volatile transistor works in a saturation state is applied to the control gate electrode of the selected transistor of a series circuit unit by a column line, thereby injecting hot electrons from the semiconductor substrate into the floating gate electrode.
    Type: Grant
    Filed: March 15, 1994
    Date of Patent: September 22, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masuoka Fujio