Abstract: A method and system for large scale Vertical-Cavity Surface-Emitting Laser (VCSEL) binning from wafers to be compatible with a Clock-Data Recovery Unit (CDRU) and/or a VCSEL driver are provided. An illustrative method of binning is provided that includes: for at least a portion of VCSELs on a wafer, measuring a set of representative parameters of the VCSELs, of predetermined DC or small-signal values, and sorting the measured VCSELs into clusters according to the measured set of representative parameters of the VCSELs; further sorting the clusters into sub-groups that comply with specifications of the VCSEL driver; and providing a feedback signal to the CDRU for equalizing control signals provided to the VCSEL driver.

Abstract: A tunable vertical-cavity surface-emitting laser (VCSEL) is provided. The VCSEL includes a VCSEL emission structure, piezoelectric material, and a piezoelectric electrode. The VCSEL emission structure includes a first reflector; a second reflector; and an active cavity material structure disposed between the first and second reflectors. The active cavity material structure includes an active region. The piezoelectric material is mechanically coupled to the VCSEL emission structure such that when the piezoelectric material experiences a mechanical stress, the mechanical stress is transferred to the active cavity material structure of the VCSEL emission structure. The piezoelectric electrode is designed to cause an electric field within the piezoelectric material.

Abstract: Several VCSEL devices for long wavelength applications in wavelength range of 1200-1600 nm are described. These devices include an active region between a semiconductor DBR on a GaAs wafer and a dielectric DBR regrown on the active region. The active region includes multi-quantum layers (MQLs) confined between the active n-InP and p-InAlAs layers and a tunnel junction layer above the MQLs. The semiconductor DBR is fused to the bottom of the active region by a wafer bonding process. The design simplifies integrating the reflectors and the active region stack by having only one wafer bonding followed by regrowth of the other layers including the dielectric DBR. An air gap is fabricated either in an n-InP layer of the active region or in an air gap spacer layer on top of the semiconductor DBR. The air gap enhances optical confinement of the VCSEL. The air gap may also contain a grating.

Abstract: Methods for forming an at least partially oxidized confinement layer of a semiconductor device and corresponding semiconductor devices are provided. The method comprises forming two or more layers of a semiconductor device on a substrate. The layers include an exposed layer and a to-be-oxidized layer. The to-be-oxidized layer is disposed between the substrate and the exposed layer. The method further comprises etching, using a masking process, a pattern of holes that extend through the exposed layer at least to a first surface of the to-be-oxidized layer. Each hole of the pattern of holes extends in a direction that is transverse to a level plane that is parallel to the first surface of the to-be-oxidized layer. The method further comprises oxidizing the to-be-oxidized layer through the pattern of holes by exposing the two or more layers of the semiconductor device to an oxidizing gas to form a confinement layer.

Abstract: Various embodiments of improved PIN-type photodiodes are provided. In an example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a second absorbing layer disposed between the first absorbing layer and the n-type contact. The first absorbing layer is characterized by a first absorption coefficient and the second absorbing layer is characterized by a second absorption coefficient. The second absorption coefficient is greater than the first absorption coefficient. In another example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a non-absorbing accelerating layer disposed between absorbing layers and non-absorbing drift layer and the n-type contact.

Abstract: A method and system for large scale Vertical-Cavity Surface-Emitting Laser (VCSEL) binning from wafers to be compatible with a Clock-Data Recovery Unit (CDRU) and/or a VCSEL driver are provided. An illustrative method of binning is provided that includes: for at least a portion of VCSELs on a wafer, measuring a set of representative parameters of the VCSELs, of predetermined DC or small-signal values, and sorting the measured VCSELs into clusters according to the measured set of representative parameters of the VCSELs; further sorting the clusters into sub-groups that comply with specifications of the VCSEL driver; and providing a feedback signal to the CDRU for equalizing control signals provided to the VCSEL driver.

Abstract: A method and system for analyzing Vertical-Cavity Surface-Emitting Lasers (VCSELs) on a wafer are provided. An illustrative method of is provided that includes: applying a stimulus to each of the plurality of VCSELs on the wafer; measuring, for each of the plurality of VCSELs, two or more VCSEL parameters responsive to the stimulus; correlating the measured two or more VCSEL parameters to define a value of a common performance characteristic; and identifying clusters of VCSELs having similar values of the common performance characteristic. The clusters of VCSELs may be determined to collectively meet or not meet an optical performance requirement defined for the VCSELs on the wafer.

Abstract: Several VCSEL devices for long wavelength applications in wavelength range of 1200-1600 nm are described. These devices include an active region between a semiconductor DBR on a GaAs wafer and a dielectric DBR regrown on the active region. The active region includes multi-quantum layers (MQLs) confined between the active n-InP and p-InAlAs layers and a tunnel junction layer above the MQLs. The semiconductor DBR is fused to the bottom of the active region by a wafer bonding process. The design simplifies integrating the reflectors and the active region stack by having only one wafer bonding followed by regrowth of the other layers including the dielectric DBR. An air gap is fabricated either in an n-InP layer of the active region or in an air gap spacer layer on top of the semiconductor DBR. The air gap enhances optical confinement of the VCSEL. The air gap may also contain a grating.

Abstract: A tunable vertical-cavity surface-emitting laser (VCSEL) is provided. The VCSEL includes a VCSEL emission structure, piezoelectric material, and a piezoelectric electrode. The VCSEL emission structure includes a first reflector; a second reflector; and an active cavity material structure disposed between the first and second reflectors. The active cavity material structure includes an active region. The piezoelectric material is mechanically coupled to the VCSEL emission structure such that when the piezoelectric material experiences a mechanical stress, the mechanical stress is transferred to the active cavity material structure of the VCSEL emission structure. The piezoelectric electrode is designed to cause an electric field within the piezoelectric material.

Abstract: A vertical-cavity surface-emitting laser (VCSEL) and method of fabrication thereof is provided. The VCSEL includes a mesa structure disposed on a substrate. The mesa structure has a first reflector stack, a second reflector stack, and an active region disposed between the first and second reflector stacks. The active region is configured to cause the VCSEL to emit light having a characteristic wavelength of 910 nanometers. The active region includes alternating layers of quantum wells and barriers, the quantum wells having high indium content (up to 18%). The VCSEL features a first contact layer disposed at least partially on a surface of the mesa structure and configured to serve as an electrical signal layer and a second contact layer disposed at least partially about the mesa structure and configured to serve as an electrical ground.