Patents by Inventor Matan Groen

Matan Groen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11171816
    Abstract: In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: November 9, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Matan Groen, Chen Gaist, Hananel Faig
  • Publication number: 20210288785
    Abstract: A method for implementing an efficient clock recovery for multilane high-speed Serializer/Deserializer (SerDes) system having M interleaved lanes, has a non-recursive architecture.
    Type: Application
    Filed: March 16, 2020
    Publication date: September 16, 2021
    Inventors: Hananel FAIG, David (Dima) ROHLIN, Matan GROEN
  • Patent number: 11108536
    Abstract: A method for implementing an efficient clock recovery for multilane high-speed Serializer/Deserializer (SerDes) system having M interleaved lanes, has a non-recursive architecture.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 31, 2021
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Hananel Faig, David (Dima) Rohlin, Matan Groen
  • Publication number: 20210044461
    Abstract: A Decision Feedback Equalizer (DFE) for filtering N symbols includes multiple processing blocks and selection logic. Each of the processing blocks includes a respective number N?<N of lookahead modules. The processing blocks are arranged in groups of L processing blocks, and each processing block in a group receives (i) N? symbols selected for the group from among the N symbols, and (ii) a predefined speculative value of a DFE output, and produces, based on the N? symbols and on the predefined speculative value, N? respective lookahead values. N??1 of the N? lookahead values are used in a chained calculation that meets a timing constraint that is not met by the chained calculation performed on N lookahead values. The selection logic selects one of the L lookahead values in each group of the L processing blocks for each of the N? symbols, and outputs N lookahead values in parallel.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 11, 2021
    Inventors: Matan Groen, Chen Gaist, Hananel Faig
  • Publication number: 20200021500
    Abstract: An apparatus for displaying status information of a network switch, which includes ports and a dedicated test port, includes an interface, one or more display elements, and circuitry. The interface is configured to connect to the network switch through a dedicated test port in the network switch that is separate from the ports. The circuitry is configured to receive from the network switch, via the interface and the dedicated test port, status information of one or more of the ports, and to display the status information using the display elements.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Inventors: Nir Einati, Matan Groen, Shay Zaretsky