Patents by Inventor Mateusz Kozlowski

Mateusz Kozlowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230139729
    Abstract: To increase the availability of a non-volatile cache for use by workloads, the non-volatile cache is dynamically assigned to workloads. The non-volatile cache assigned to a workload can be reduced or increased on demand. A cache space manager ensures that the physical non-volatile cache is available to be assigned prior to assigning. A workload analyzer recognizes a sequential or random workload and requests to reduce the cache space assigned for the sequential or random workload. The workload analyzer recognizes a locality workload, waits until cache space is available in the non-volatile cache and requests an increase of cache space for the locality workload.
    Type: Application
    Filed: December 28, 2022
    Publication date: May 4, 2023
    Inventors: Mariusz BARCZAK, Wojciech MALIKOWSKI, Mateusz KOZLOWSKI, Lukasz LASEK, Artur PASZKIEWICZ, Krzysztof SMOLINSKI
  • Publication number: 20230076365
    Abstract: A method is described. The method includes constructing a bitmap having a first dimension organized into bins of logical block addresses (LBA bins) and a second dimension organized into bins of physical block addresses (PBA bins). Coordinates of the bitmap indicate whether respective physical blocks of non volatile memory within one or more SSDs that fall within a particular PBA bin are being mapped to by an LBA that falls within a particular one of the LBA bins. The method includes using the bitmap during a rebuild of an LBA bin of an LBA/PBA table to avoid reading meta data for physical blocks that are not mapped to by an LBA that falls within the LBA bin.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 9, 2023
    Inventors: James R. HARRIS, Benjamin WALKER, Mateusz Kozlowski, Kapil KARKRA, Artur Paszkiewicz
  • Publication number: 20230051328
    Abstract: Systems, apparatuses, and methods provide for a memory controller to manage a tiered memory including a zoned namespace drive memory capacity tier. For example, a memory controller includes logic to translate a standard zoned namespace drive address associated with a user write to a tiered memory address write. The tiered memory address write is associated with the tiered memory including the persistent memory cache tier and the zoned namespace drive memory capacity tier. A plurality of tiered memory address writes are collected, where the plurality of tiered memory address writes include the tiered memory address write and other tiered memory address writes in the persistent memory cache tier. The collected plurality of tiered memory address writes are transferred from the persistent memory cache tier to the zoned namespace drive memory capacity tier, via an append-type zoned namespace drive write command.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 16, 2023
    Inventors: Mariusz Barczak, Wojciech Malikowski, Mateusz Kozlowski, Lukasz Lasek, Artur Paszkiewicz, Kapil Karkra