Patents by Inventor Matheus GIBILUKA

Matheus GIBILUKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230325091
    Abstract: A circular First-In-First-Out (FIFO) Buffer is provided as an intuitive interface between synchronous domains and asynchronous domains by incorporating flow control and standard synchronizers to allow for serialization and deserialization that can be carried out as an asynchronous-to-synchronous transition, a synchronous-to-asynchronous transition, or even a fully asynchronous circular transition. Each of these configurations may also include single read or multiple-read operations.
    Type: Application
    Filed: February 6, 2023
    Publication date: October 12, 2023
    Inventors: Stefano Giaconi, Giacomo Rinaldi, Matheus Gibiluka, David Fong
  • Publication number: 20230251983
    Abstract: A hybrid asynchronous network-on-chip (NoC) optimized for artificial intelligence workloads utilizes a “tile” layout methodology with a plurality of tiles, each tile including an asynchronous node with a plurality of input ports and output ports for communicating with adjacent asynchronous nodes on adjacent tiles, along with a processor input port and processor output port configured to transport data from an asynchronous processor, but capable of being customized to transport data between a synchronous processor through the implementation of modular synchronous-to-asynchronous and asynchronous-to-synchronous first-in-first-out (FIFO) buffers. The asynchronous NoC is able to efficiently satisfy the interconnect traffic requirement of modern machine learning systems, eliminating the need for a global clock distribution and enabling unlimited scalability while providing high throughput and minimal latency performance.
    Type: Application
    Filed: February 6, 2023
    Publication date: August 10, 2023
    Inventors: Stefano Giaconi, Giacomo Rinaldi, Matheus Gibiluka, David Fong
  • Publication number: 20220358069
    Abstract: System and methods for an Advance Centralized Chronos Network on Chip (ACC-NoC) design are disclosed. The ACC-NoC is able to efficiently satisfy interconnect traffic requirements of modern Systems of Chip and simplify top level timing closure while providing high throughput and low latency. The ACC-NoC in a System on Chip may include a centralized intelligent switch and arbitration engine communicatively coupled to different intellectual property (IP) blocks through series of one or more Chronos Channels which transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic.
    Type: Application
    Filed: May 6, 2022
    Publication date: November 10, 2022
    Inventors: Stefano GIACONI, Giacomo RINALDI, Matheus GIBILUKA