Abstract: Multiple product terms (PTs) are combined with a multiple-input look-up table (LUT) to form a LUT-based Boolean term (LBT) that generates a Boolean output. Multiple LBTs are combined with one or more sum terms to form an enhanced generic logic block (EGLB) that can be programmed to operate, e.g., as a sum-of-products structure, where the EGLB structure can be repeated within a programmable logic device (PLD). Different multi-bit Boolean functions can be implemented in a single pass through each EGLB, with fewer resources then prior art structures. Multiple LBTs can be combined with other logic to form combined LBTs (CLBTs). This invention can provide improved Boolean function packing density compared to existing PLD architectures and/or shorter delays for a comparable packing density.

Abstract: A PLD circuit configuration is provided to use less product term lines than a typical PLD to perform an OR operation without using an OR gate. In one embodiment, an inverter is provided between the output of one product term line and the input of an OR gate. The inverter enables the one product term provided to it to provide an OR operation. This is because when two or more elements are ANDed in a product term, inverting the product term creates an OR operation with the elements inverted. With an OR operation provided using a single product term and inverter, less product term lines are needed when performing some operations. In another embodiment, an OR gate output is provided to the first input of a look up table (LUT), while a single product term line is provided to a second input of the LUT. The LUT can be programmably configured to perform a number of Boolean logic functions, such as an OR gate, an XOR gate, etc.