Patents by Inventor Mathew B. Nazareth

Mathew B. Nazareth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states
    Patent number: 7299370
    Abstract: A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: November 20, 2007
    Assignee: Intel Corporation
    Inventors: Varghese George, Mark A. Newman, Sanjeev Jahagirdar, Inder M. Sodhi, Tanjeer R. Khondker, Mathew B. Nazareth, John B. Conrad
  • Selecting a first clock signal based on a comparison between a selected first clock signal and a second clock signal
    Patent number: 7043654
    Abstract: According to some embodiments, a potential clock signal is selected based on a comparison between a selected first clock signal and a second clock signal.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: Tanveer R. Khondker, Mathew B. Nazareth
  • Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states
    Publication number: 20040255176
    Abstract: A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 16, 2004
    Inventors: Varghese George, Mark A. Newman, Sanjeev Jahagirdar, Inder M. Sodhi, Tanveer R. Khondker, Mathew B. Nazareth, John B. Conrad
  • Selecting a first clock signal based on a comparison between a selected first clock signal and a second clock signal
    Publication number: 20040128579
    Abstract: According to some embodiments, a potential clock signal is selected based on a comparison between a selected first clock signal and a second clock signal.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Inventors: Tanveer R. Khondker, Mathew B. Nazareth
  • Fingered capacitor in an integrated circuit
    Patent number: 6385033
    Abstract: A fingered capacitor in an integrated circuit. A first capacitor element is formed in a first layer of an integrated circuit (IC) die. The first capacitor element includes a positive plate and a negative plate. Each of the positive and negative plates of the first capacitor element has a plurality of fingers interdigitated with the fingers of the other of the positive and negative plates of the first capacitor element. The fingers are separated by a dielectric. The interdigitated fingers cooperate to generate fringe capacitance between neighboring fingers. A plurality of capacitor elements having interdigitated fingers can be provided in adjacent layers of the IC die.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: May 7, 2002
    Assignee: Intel Corporation
    Inventors: Jahanshir J. Javanifard, Hari R. Giduturi, Mathew B. Nazareth
  • Method and apparatus for varying a clock frequency on a phase by phase basis
    Patent number: 6127858
    Abstract: A circuit to vary a frequency of an input clock is disclosed. The circuit includes a delay generator to generate at least two delayed clocks from the input clock and a select circuit coupled to receive the at least two delayed clocks and provide an output clock from one of the at least two delayed clocks. The select circuit switches the output clock from the one of the at least two delayed clocks to the other of the at least two delayed clocks on a first edge.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: October 3, 2000
    Assignee: Intel Corporation
    Inventors: Jason C. Stinson, Edwin R. Lilya, Mathew B. Nazareth