Abstract: Implementations described herein relate to run-time management of a serverless function in a serverless computing environment. In some implementations, a method includes receiving, at a processor, based on historical run-time invocation data for the serverless function in the serverless computing environment, a first number of expected invocations of the serverless function for a first time period, determining, by the processor, based on the first number of expected invocations of the serverless function for the first time period, a second number of warm-up invocation calls to be made for the first time period, and periodically invoking the second number of instances of an extended version of the serverless function during the first time period, wherein the extended version of the serverless function is configured to load and initialize the serverless function and terminate without executing the serverless function.

Abstract: Implementations described herein relate to run-time management of a serverless function in a serverless computing environment. In some implementations, a method includes receiving, at a processor, based on historical run-time invocation data for the serverless function in the serverless computing environment, a first number of expected invocations of the serverless function for a first time period, determining, by the processor, based on the first number of expected invocations of the serverless function for the first time period, a second number of warm-up invocation calls to be made for the first time period, and periodically invoking the second number of instances of an extended version of the serverless function during the first time period, wherein the extended version of the serverless function is configured to load and initialize the serverless function and terminate without executing the serverless function.

Abstract: A method includes executing, multiple times, a target application with at least one test input dataset to obtain multiple test output datasets. The test output data sets each include multiple field values for multiple fields. The method further includes comparing the field values with at least one validated output dataset to assign the fields into a match class, an ignore class, and an unknown class, extracting, from the comparing, a field property for a first subset of the fields in the match class, and generating a test result by adding, to the test result, whether a first subset of the field values corresponding to the first subset of the fields satisfies a corresponding field property, and ignoring a second subset of the a second subset of fields classified in the ignore class. The method further includes presenting the test result.

Abstract: A processor may receive record data describing at least one interaction between a client and a production environment providing a software service. The processor may receive company dump data describing a context of the production environment during the at least one interaction. The processor may construct at least one simulation of at least one version of the software service including the context. The processor may replay the at least one interaction within the at least one simulation to generate at least one replay result. The processor may identify at least one problem with the at least one version of the software service based on the at least one replay result.

Abstract: Global ready financial applications are provided that are dynamically composed using application independent global ready financial assets so that a single global ready financial application, once created, can be operationally and functionally optimized for multiple supported regions to be used by any party, in any, or all, of the multiple supported regions.

Abstract: A method and apparatus to provide a capacitance to a design an integrated circuit is described. In one embodiment, the method receive a layout of the integrated circuit and applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model to capture a first capacitance of a device having a plurality of first conductors and a second type canonical model to capture a second capacitance between at least a portion of the device and one or more second conductors of the integrated circuit. The method further includes determining a capacitance for the layout based on the applying.

Abstract: A method and apparatus to provide a capacitance to a design an integrated circuit is described. In one embodiment, the method receive a layout of the integrated circuit and applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model to capture a first capacitance of a device having a plurality of first conductors and a second type canonical model to capture a second capacitance between at least a portion of the device and one or more second conductors of the integrated circuit. The method further includes determining a capacitance for the layout based on the applying.

Abstract: A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a device having a plurality of conductors, and a canonical model to capture a capacitance between at least a portion of the device and one or more other conductors of the integrated circuit. The canonical hierarchical models can be applied to a layout of the integrated circuit. A capacitance for the layout can be determined based on the canonical hierarchical models.

Abstract: A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a device having a plurality of conductors, and a canonical model to capture a capacitance between at least a portion of the device and one or more other conductors of the integrated circuit. The canonical hierarchical models can be applied to a layout of the integrated circuit. A capacitance for the layout can be determined based on the canonical hierarchical models.

Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

Abstract: One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file. The system then combines the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.

Abstract: In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.

Abstract: The present invention presents a hybrid approach for manufacturability analysis that integrates both a rules-based approach and a models-based approach. For example, a rules-based analysis can be used to optimize the performance of a model-based analysis. The rules analysis can be used to identify specific areas of a layout that can then be analyzed in detail using models. This approach provides numerous advantages. It allows the models-based analysis tool to concentrate upon portions of the layout that requires greater attention and allocate fewer resources towards the areas less critical to the yield.

Abstract: One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file. The system then combines the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.

Abstract: Methods and systems for integrating both models and rules into a verification flow to address both of these issues. Models are employed to perform simulations to provide more accurate verification results. In addition, the lithography simulation results can be used to fine-tune the rules themselves to provide a more realistic check upon circuit designs.

Abstract: Methods and systems for the integration of models and accurate predictions to score the circuit design, which translates to a more accurate and less complex yield prediction. In the present inventive approach, the computer-implemented methods and systems use at least one processor that is configured for performing at least predicting a physical realization of a layout design based at least in part on one or more model parameters, determining one or more hotspots associated with the layout design, determining a score for each of the one or more hotspots associated with the layout design, and categorizing the one or more hotspots according to at least the score in some embodiments. In some embodiments, the methods or the systems further use at least one processor for the act of determining one or more hotspots by using at least the design intent or the manufacturing information.

Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.