Abstract: In a communication system that utilizes DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), carrier channel allocations may be updated as follows. At periodic intervals, the primary site requests updating bit loading information from the secondary sites. Upon receiving the updated bit loading information, the primary site (102) determines an updated call bit loading table for each active call. From this, the primary site (102) determines whether current carrier channel allocation provides sufficient bandwidth. When the current carrier channel allocation does not provide the sufficient bandwidth, the primary site modifies the current carrier channel allocation to meet the bandwidth requirements.

Abstract: A line driver (10) includes a first p-channel FET (12) and two n-channel FETs (14-16), wherein one of the n-channel FETs functions as a blocking FET (16). The p-channel FET (12) is coupled to the supply voltage (26) and the blocking FET (16), while the other n-channel FET (14) is coupled to a supply return (28) and the blocking FET (16). An output (30) is provided between the n-channel FET (14) and the blocking FET (16), while inputs (20-22) are provided to the p-channel FET (12) and the n-channel FET (16). In operation, the inputs (20-22) are supplied to the FETs at a given rate such that either the p-channel or the n-channel FET is "on". To ensure a maximum output swing when the p-channel FET is on, the blocking FET (16) is sourced by a charge pump (18).

Abstract: In a communication system that utilizes DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), carrier channel allocations may be performed as follows. When a call request is received, the primary site (102) determines the number of required bits based on the bandwidth requirements of the call. Next, the primary site (102) determines whether the maximum bit loading of a given carrier channel exceeds the number of required bits. If yes, the primary site allocates a carrier channel having a bit loading that most closely matches the number of required bits. If no, the primary site allocates the carrier channel having the maximum bit loading to the call, then calculates a remaining number of required bits. From here, the primary site repeats the above process until a sufficient number of carrier channels have been allocated to the call.

Abstract: A reference current source (38) and a matched reference transistor (40) are provided as part of a current limiting circuit, wherein the matched reference transistor (40) is scaled, electrically matched, and physically located in close proximity to an on-chip switching transistor (16) of a DC--DC converter. By serially coupling the reference current source (38) to the reference transistor (40), a reference signal (48), which is equal to the voltage across the reference transistor (40), is generated. The reference signal (48) is compared to the voltage across the switching transistor (16) while the switching transistor (16) is conducting. When the voltage across the switching transistor (16) exceeds that across reference transistor (40), the gate drive to the switching transistor (16) is disabled for the remainder of the current conductive phase.

Abstract: The present invention provides a circuit (10) and method for sampling a single-ended signal and then converting the single-ended signal to a differential signal. After the single-ended signal is converted to a differential signal, then the offset voltage and low frequency noise of an operational amplifier (38) are subtracted from the differential signal using analog techniques. The subtraction operation effectively removes an operational amplifier's offset voltage and a low frequency noise from being a source of error in the differential output signal of the circuit.

Abstract: A fully differential line driver circuit (25) includes an input differential amplifier (26) and double-ended differential amplifiers (27, 28). A first output driver stage (29) includes a pair of series connected transistors (30, 31), and a second output driver stage includes a pair of series connected transistors (33, 34). The differential amplifiers (27, 28) provide bias and signals voltages to the gates of the series connected transistors (30, 31, 33, 34). The output stages (29, 32) provide differential output signals for driving a low impedance load. The clamping circuits (35-38) control overlap currents in the output stages (29, 32). Common-mode feedback is used to ensure a common-mode voltage of the differential output signals remains at a predetermined voltage to ensure maximum signal swing and thus, maximum efficiency.

Abstract: A self-biased cascode current mirror includes a current mirror (60), and a cascode bias generator (50). The cascode bias generator (50) includes a resistor (51) to provide a bias voltage for the current mirror (60). The current mirror (60) includes cascode transistor (64) and two mirror transistors (62, 63). The bias voltage is approximately equal to a minimum saturation voltage of the cascode transistor (64) plus a gate-source voltage of the transistor (63) of the current mirror (60). The self-biased cascode current mirror (60) has a high output impedance and high voltage swing while providing low power consumption and requiring a small layout area.

Abstract: A digital-to-analog converter (10) uses series-connected resistors (55-59) to implement conversion of most significant bits of a digital input signal to an equivalent analog output signal. Current sources (22-26) are used to implement conversion of least significant bits of the digital input signal to the analog output signal. After making a binary-to-thermometer code conversion of the least significant bits, first logic circuitry (70) provides control signals (SI) for controlling the switching of each of the current sources to either a first (42) or a second (44) node. After making a binary to `one of` code conversion of the most significant bits, second logic circuitry (86) provides control signals (SR) for respectively switching the first and second nodes to any two resistor nodes of the resistors. The resistors are connected between a reference voltage terminal and a third node where the analog output signal is developed.

Abstract: A digital-to-analog converter (10) performs two distinct conversions (12,59) of most significant bits (MSBs) and least significant bits (LSBs), respectively, of a digital input signal and uses the conversion results to provide an equivalent analog output. A plurality of current sources (34-36) is controlled by a thermometer code equivalent value of the most significant bits to provide a first input current to an output stage (22). A plurality of resistors (60-63) is controlled by a binary to `one of` equivalent of the least significant bits to provide a second input current to the output stage. The output stage (22) converts a combination of the first and second input currents to the analog output.

Abstract: A differential amplifier (60,60') enhances common-mode stability by making two nodes (86,87) of a first stage low common-mode impedance nodes and thus shifting a common-mode dominant pole from the two nodes (86,87). The first stage includes an input portion (80,80') and a differential load (110,110'). The input portion (80,80') provides first and second currents respectively to the differential load (110,110') in response to a differential input voltage. The first and second currents have a differential component and a common-mode component. The differential load (110,110') converts the differential and common-mode components of the first and second currents into differential and common-mode voltages, respectively, and provides a high impedance to the differential component and a low impedance to the common-mode component.

Abstract: An output driver circuit with improved output stage clamping comprises an input stage, an output stage, and a clamping circuit. The input stage amplifies a difference between an input signal and a reference signal to provide first and second output signals for driving gates of first and second transistors which together form the output stage. The first and second transistors are serially coupled between first and second power supply voltage terminals and provide an output signal. The clamping circuit clamps the first signal at a predetermined gate-to-source voltage below the first power supply voltage, and clamps the second signal at a predetermined gate-to-source voltage above the second power supply voltage terminal. The clamp voltages are maintained by matching current densities and bias conditions between the first and second transistors, and corresponding transistors in the clamping circuit.

Abstract: An analog-to-digital converter utilizes both a successive approximation register and a current steering circuit within a digital-to-analog converter to achieve an improved conversion speed, and improved resolution for a predetermined amount of power. The current steering circuit, which is controlled by the successive approximation register, connects constant current sources to current source loads to produce a differential signal output. By steering current from the differential current source loads to the constant current sources, a signal difference resolves at the output of the digital-to-analog converter faster and with greater resolution.

Abstract: A voltage that is proportional to a differential input voltage is applied across two resistors. Each resistor produces a current that is proportional to the input voltage. The current from each resistor flows through an associated current mirror. Each current mirror produces a current equal to the current flowing through the associated resistor. The current produced by each current mirror becomes an output current that is proportional to the input voltage.

Abstract: A stable digitally controlled driver circuit having an output stage with two series-coupled transistors of opposite conductivity type. The driver circuit operates as an analog amplifier with a digitally controlled output stage. The digital control is provided by control transistors which selectively alternately couple a gate of each transistor in the output stage to the output of a differential amplifier. An output signal of the driver circuit is fed back to the input of the differential amplifier to provide a voltage gain determined by the feedback configuration. When both of the series-coupled transistors in the output stage are made nonconductive, the driver circuit's output is in a high impedance state thereby providing a three-state output.

Abstract: A circuit provides power supply noise cancellation by utilizing a correction capacitor coupled to a compensation input of the circuit. Power supply noise is introduced into an output of the circuit by inadvertently coupling an error voltage thru a capacitor to the output as a result of power supply voltage variation. A compensation charge is produced by the correction capacitor and a sub-amplifier of the circuit which, through charge transfer, cancels the error voltage at the output, thereby providing an output signal having substantially reduced power supply noise.

Abstract: A bandgap reference circuit providing a continuous output reference voltage. The bandgap reference circuit comprises an operational amplifier, an output circuit, and a compensation circuit. The operational amplifier receives a first input signal and a second input signal and provides an output signal in response to a difference in voltage between the first input signal and the second input signal. The output circuit receives the output of the operational amplifier and provides an output reference voltage. The output circuit provides the first input signal and the second input signal to the operational amplifier in such a way as to maintain the output reference voltage at a substantially constant value. The compensation circuit provides a current to the output circuit to compensate for currents conducted from the bases of transistors in an input stage of the operational amplifier, thereby making the output reference voltage more stable.

Abstract: A method for directly providing a conversion of an analog input signal to a digital signal in two's complement code with a sampled data converter. Positive and negative reference voltages and an analog ground voltage are required. After a sign bit determination of the input signal is made, the data converter is coupled between either a first pair of reference voltages or a second pair of reference voltages depending upon the sign bit. The first pair of reference voltages comprises the positive reference and ground reference, and the second pair of reference voltages comprises the ground reference and a negative reference. By selectively coupling the chosen reference voltages to the converter, a converter may directly output two's complement code.

Abstract: A switched capacitor sample-and-hold circuit which compensates offset voltage error and switch feedthru error while having a one hundred percent duty cycle is provided. Two amplifiers are utilized. A first operational amplifier is disconnected from a second operational amplifier while being autozeroed. An input voltage is sampled onto an input capacitor. The input capacitor is disconnected from the input voltage and then coupled to the second operational amplifier which is in a unity gain configuration. After the sampled input voltage is charged onto an output load, the first operational amplifier is disconnected from the second operational amplifier and the sampling process is repeated. The second operational amplifier is also offset voltage compensated by the first operational amplifier.

Abstract: An N bit converter, where N is an integer, is provided for effecting A/D and D/A conversions by utilizing a capacitor array and a resistor voltage divider string. The converter may be linear or nonlinear and the structure remains monotonic independent of the accuracy of the converter. Although monotonic, device count is minimized and only 2.sup.(N/2) stages are required to implement an N bit linear converter. Reduction of the number of circuit elements is achieved, in part, by shared use of decode circuitry for the most significant and least significant bits of the N bits.