Patents by Inventor Mathias Boman

Mathias Boman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8893061
    Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: November 18, 2014
    Assignee: Synopsys, Inc.
    Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
  • Publication number: 20140189616
    Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage.
    Type: Application
    Filed: March 3, 2014
    Publication date: July 3, 2014
    Applicant: Synopsys, Inc.
    Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
  • Patent number: 8667429
    Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 4, 2014
    Assignee: Synopsys, Inc.
    Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
  • Patent number: 8341559
    Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: December 25, 2012
    Assignee: Synopsys, Inc.
    Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
  • Publication number: 20120054693
    Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 1, 2012
    Applicant: SYNOPSYS, INC.
    Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
  • Patent number: 8065638
    Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: November 22, 2011
    Assignee: Synopsys, Inc.
    Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
  • Publication number: 20100198875
    Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Applicant: SYNOPSYS, INC.
    Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall