Patents by Inventor Mathias Gruetzner

Mathias Gruetzner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test circuit and method for interconnect testing of chips
    Patent number: 6219811
    Abstract: The invention relates to a test circuit, and a test method that provides testing for interconnect capability for chips (100, 110). Each of the chips (100, 110) comprises combinational logic (172, 173, 160, 161, 176, 177) as well as a plurality of scan chains (170, 171, 150, 151, 174, 175). Test data is shifted into the scan chains from pattern generators (180, 181) and is then transmitted from a selected sending chip (100) via its transceiver means (130) to the receiving chip (110). The chip (100) is selected by the selector (120) which is located on chip (100). During an interconnect test sequence, different chips in the test system are selected by the selector (120) for testing.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: April 17, 2001
    Assignee: International Business Machines Corporation
    Inventors: Mathias Gruetzner, Wilfred Hartmann, Cordt-Wilhelm Starke