Abstract: The present disclosure relates to an electronic instrument for analyzing a device-under-test, DUT, comprising: a digital signal generator configured to generate a test signal having a first frequency; a signal output unit which is connected to the DUT, wherein the signal output unit is configured to convert the test signal to an analog signal and to forward said signal to the DUT; a signal input unit which is connected to the DUT and which is configured to receive a DUT response signal which is based on the test signal, wherein the signal input unit is configured to digitalize the DUT response signal; a signal processing circuity configured to receive the digitalized DUT response signal and to downconvert said signal using the first frequency of the test signal; and an analyzing unit configured to analyze the downconverted DUT response signal in order to determine a transfer function, an impedance and/or a loop stability of the DUT.

Abstract: A signal analysis method is described. The signal analysis method includes: receiving a time-and-value discrete input signal, the input signal being associated with a signal source; determining at least one jitter component of the input signal; determining a step response based on the input signal, the step response being associated with at least the signal source; determining a counter function based on the step response, the counter function being configured to cancel error terms in a finite-time transform of the step response to frequency domain; superposing the step response and the counter function, thereby obtaining a modified step response; and transforming the modified step response to frequency domain, thereby obtaining a transfer function being associated with at least the signal source. Further, a signal analysis module for analyzing a time-and-value discrete input signal being associated with a signal source is described.

Abstract: A signal analysis method is described. The signal analysis method includes: receiving a time-and-value discrete input signal, the input signal being associated with a signal source; determining at least one jitter component of the input signal; determining a step response based on the input signal, the step response being associated with at least the signal source; determining a counter function based on the step response, the counter function being configured to cancel error terms in a finite-time transform of the step response to frequency domain; superposing the step response and the counter function, thereby obtaining a modified step response; and transforming the modified step response to frequency domain, thereby obtaining a transfer function being associated with at least the signal source. Further, a signal analysis module for analyzing a time-and-value discrete input signal being associated with a signal source is described.

Abstract: The present disclosure relates to a method of reducing a noise induced signal drift. The method comprises: receiving an input signal; recording a waveform of the input signal; and determining an antiderivative of the waveform by optimizing a derivative of the antiderivative to be determined and an absolute deviation of the antiderivative to be determined. Further, the present disclosure relates to a test instrument for analyzing an input signal.

Abstract: A system includes a first node that generates a first clock signal having a frequency, generates a plurality of data packets, modifies the data packets to include data indicative of time and phase information associated with the first node, and transmits the data packets. A second node receives the plurality of data packets and the first clock signal, determines the time and phase information based on the plurality of data packets, determines the frequency based on the first clock signal, and generates at least one of a second clock signal and a local time based on the time and phase information and the frequency of the first clock signal.

Abstract: A system includes a first node that generates a first clock signal having a frequency, generates a plurality of data packets, modifies the data packets to include data indicative of time and phase information associated with the first node, and transmits the data packets. A second node receives the plurality of data packets and the first clock signal, determines the time and phase information based on the plurality of data packets, determines the frequency based on the first clock signal, and generates at least one of a second clock signal and a local time based on the time and phase information and the frequency of the first clock signal.

Abstract: Data transmission memory (1) for the transmission of data packets between subscribers T with a pointer address memory (2) for storing chained subscriber-pointer address lists, comprising pointer addresses, for each subscriber; a plurality of subscriber state registers (12), which in each case store the state of an associated subscriber-pointer address list; a data memory (3) for storing data blocks which can be addressed by the pointer addresses; and with a memory controller (4) for controlling the pointer address memory (2) and the data memory (3).

Abstract: A method for operating a switching system for data packets includes providing a switching system having inputs and outputs, temporarily storing data packets at an input of the switching system where, when each data packet arrives, merely sending a message to an output of the switching system at the input and placing the message into a queue at the output. The method combines advantages of temporary storage at the input with the advantages of temporary storage at the output, without having to accept the disadvantages of one of such systems.

Abstract: A method for switching a plurality of packet-oriented signals and an apparatus for performing the method includes supplying a signal to port units, each having ports, at one port, some ports, or all ports. A signal is connected from one port to another port of another unit by a central switching unit. Signal transmission therebetween is performed by transmission of data blocks. Each port unit ascertains the address information item for each packet supplied and uses the item to determine the appropriate receiving port unit. Each port unit stores the data packet in a buffer memory, compiles availability information and transmits it to the switching unit, which evaluates availability and ascertains further transmission without blocking occurring. The switching unit connects the necessary paths between the transmitting and receiving port units and transmits the packets/cells through the paths.

Abstract: Data transmission memory (1) for the transmission of data packets between subscribers T with a pointer address memory (2) for storing chained subscriber-pointer address lists, comprising pointer addresses, for each subscriber; a plurality of subscriber state registers (12), which in each case store the state of an associated subscriber-pointer address list; a data memory (3) for storing data blocks which can be addressed by the pointer addresses; and with a memory controller (4) for controlling the pointer address memory (2) and the data memory (3).