Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.

Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.

Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.

Abstract: The invention relates to a method of testing interconnections in integrated circuit (IC) assemblies. Hereto, a test signal is applied to an IC pin (110) providing an input terminal to the interconnection. In known methods, such as the boundary-scan method, a response signal is measured on an output terminal of the interconnection, provided by a further IC pin. According to the invention, however, a response signal is evaluated which is generated on the same terminal (110) as to which the test signal is applied. This has the advantage that the method of the invention can be applied when only one end of the interconnect to be tested can be supplied with appropriate test hardware. The method is particularly suited for testing a capacitance (195) between an IC pin (110) and a supply line, e.g. a ground line.

Abstract: The invention relates to a method of testing interconnections in integrated circuit (IC) assemblies. Hereto, a test signal is applied to an IC pin (110) providing an input terminal to the interconnection. In known methods, such as the boundary-scan method, a response signal is measured on an output terminal of the interconnection, provided by a further IC pin. According to the invention, however, a response signal is evaluated which is generated on the same terminal (110) as to which the test signal is applied. This has the advantage that the method of the invention can be applied when only one end of the interconnect to be tested can be supplied with appropriate test hardware. The method is particularly suited for testing a capacitance (195) between an IC pin (110) and a supply line, e.g. a ground line.

Abstract: A device which includes a first integrated circuit and a second IC for applying a fixed logic value to an input of the first integrated circuit. A conventional implementation uses pull-up and pull-down resistors, but these resistors necessitate an additional step and additional elements for the testing of the relevant interconnections. The device is improved in that an output of the second IC, which outputs the logic value during normal operation, is controlled via test logic during testing. As a result, the interconnections between the output of the second IC and the input of the first IC are tested in the same way and as part of the testing of the other interconnections between the first and second integrated circuits.

Abstract: The invention relates to an arrangement for testing, by way of the Boundary Scan Test method, carriers on which there are provided a number of ICs with BST logic and a number of ICs without BST logic. The arrangement comprises a connection module enabling the testing of such carriers also when the ICs without BST logic are fast in comparison with the neighboring BST logic.

Abstract: A testable circuit comprises a signal path having a time-dependent response behavior (for example, a high-pass filter behavior). The signal path is tested for faults. To this end, the circuit is switched to a test mode in which the signal path is isolated from other signal paths. Subsequently, a test signal containing a signal transition is applied to the input of the signal path and it is tested whether the signal on the output of the signal path at any instant exceeds a threshold level during a predetermined time interval after the transition. The result is loaded into a register and read from the circuit.

Abstract: A method for generating test patterns to detect an electric shortcircuit, a method for testing electric circuitry while using test patterns so generated, and a tester device for testing electric circuitry with such test patterns. If electric circuitry comprises a plurality of separate nets, a short circuit between an arbitrary pair of nets may be detected by driving the first net at logic zero and the second net at logic one. Measuring the two effective net potentials of the pair of nets will then reveal the short in that two equal potentials would occur. In the case of CMOS technology the driving patterns should also comprise the inverse of the combination above, and also for each pair of nets the number of non-identical overall patterns having the particular 1/0 and 0/1 combinations should be guaranteed and adjustable. The total number of patterns should be minimal. In a test pattern matrix, each column is a single overall pattern; each row is the sequence of signals for the net in question.

Abstract: Additional logic is added to a sequential finite-state machine circuit having a self-initialing behavior so that the circuit can be simulated. From any state, a rest state is reached by way of a given sequence of values of an input signal. Transitions between states of the finite-state machine are realized by the additional logic, such that the simulated circuit realizes the transition from an unknown state to a known, absorbing state in steps.