Patents by Inventor Mathias Pfeiffer

Mathias Pfeiffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030215129
    Abstract: By rendering a special test image and applying flat-field correction for a device under test (DUT) non-uniformity, the E-O response of a reflective LCOS microdisplay can be quickly determined through an image processing algorithm. The measurement is made in a spatial domain instead of in a temporal domain. From the measurement, the driving voltage of maximum brightness, Vbright, can be determined. The use of Vbright enhances the visibility of pixel and sub-pixel defects to the test system. Other defect visibility enhancements are achieved through appropriate sampling rate, optical axis rotation and improved parallelism between the DUT and the CCD sensor camera. By modeling a sub-pixel defect as a local non-uniformity, a near neighborhood algorithm may be used for detection. The neighborhood algorithm does not rely on the alignment between the display pixels and the camera pixels.
    Type: Application
    Filed: December 6, 2002
    Publication date: November 20, 2003
    Applicant: THREE-FIVE SYSTEMS, INC.
    Inventors: Qingsheng J. Yang, Dan D. Hoffman, Peter A. Smith, Mathias Pfeiffer
  • Patent number: 5754544
    Abstract: A switching network for the pick-up and forwarding of data streams has a plurality of input line units and output line units which respectively accept or output data streams in fixed multiplex frames, and which are connected in common to an exchange bus. A respective data memory whose memory cells are individually allocated to the bit places of a multiplex frame for the individual output line units is provided in the input line units. The data bits of a multiplex frame are entered bit-by-bit into the corresponding memory cells in the data memories based on the criterion of allocation information. The memory cells of the individual data memories are synchronously driven by a central control unit in a fixed sequence for the output of stored data bits onto the exchange bus. Only one of the data bits corresponding to one another in the individual data memories is thereby enabled based on the criterion of enable information, whereas the others are masked.
    Type: Grant
    Filed: February 13, 1996
    Date of Patent: May 19, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventor: Mathias Pfeiffer