Patents by Inventor Mathieu Perin
Mathieu Perin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11545982Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (??LO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.Type: GrantFiled: March 23, 2022Date of Patent: January 3, 2023Assignee: NXP B.V.Inventors: Mathieu Perin, Stefano Dal Toso, Khurram Waheed, Claudio Gustavo Rey
-
Patent number: 11489532Abstract: An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.Type: GrantFiled: April 27, 2021Date of Patent: November 1, 2022Assignee: NXP B.V.Inventors: Mathieu Périn, Stefano Dal Toso
-
Publication number: 20220321132Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (??LO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.Type: ApplicationFiled: March 23, 2022Publication date: October 6, 2022Inventors: Mathieu Perin, Stefano Dal Toso, Khurram Waheed, Claudio Gustavo Rey
-
Publication number: 20220311446Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.Type: ApplicationFiled: March 18, 2022Publication date: September 29, 2022Inventors: Mathieu Perin, Stefano Dal Toso, Khurram Waheed, Claudio Gustavo Rey
-
Patent number: 11437985Abstract: A duty cycle correction circuit (DCCC) for a multi-modulus frequency divider, the DCCC comprising: a corrector chain comprising a plurality of flip-flops each configured to receive one of the internal signals; and at least one delay selection logic element, each configured to receive an output signal from different ones of the flip-flops and the output of each delay selection logic element is based on the received output signal and the division factor; the DCCC is configured such that: a first state change in its output signal is defined by a transition to a first logic state of one of the internal signals; and a second state change in its output signal is based on a transition to a second logic state of one of the internal signals after a delay period, wherein the duty cycle of the output signal is based on the delay period.Type: GrantFiled: October 1, 2021Date of Patent: September 6, 2022Assignee: NXP USA, Inc.Inventors: Mathieu Vallet, Stefano Dal Toso, Mathieu Périn
-
Publication number: 20220263512Abstract: An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.Type: ApplicationFiled: April 27, 2021Publication date: August 18, 2022Inventors: Mathieu Périn, Stefano Dal Toso
-
Patent number: 11196429Abstract: Locking time for a phase-locked loop is decreased by selectively controlling a division value of the feedback divider during the first division cycle to reduce the initial phase error. The division value of the feedback divider during the first division cycle is selectively set such that the locking phase relationship between the two phase detector input signals is achieved at the end of the first division cycle.Type: GrantFiled: July 27, 2020Date of Patent: December 7, 2021Assignee: NXP USA, Inc.Inventors: Stefano Dal Toso, Mathieu Perin
-
Patent number: 11114978Abstract: A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus includes a plurality of unit variable reactance structures including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.Type: GrantFiled: October 2, 2020Date of Patent: September 7, 2021Assignee: NXP B.V.Inventors: Mathieu Perin, Stefano Dal Toso
-
Publication number: 20210126584Abstract: A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus comprises includes a plurality of unit variable reactance structures comprising including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals comprising including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator comprises includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method comprises includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.Type: ApplicationFiled: October 2, 2020Publication date: April 29, 2021Inventors: Mathieu Perin, Stefano Dal Toso
-
Publication number: 20210067164Abstract: Locking time for a phase-locked loop is decreased by selectively controlling a division value of the feedback divider during the first division cycle to reduce the initial phase error. The division value of the feedback divider during the first division cycle is selectively set such that the locking phase relationship between the two phase detector input signals is achieved at the end of the first division cycle.Type: ApplicationFiled: July 27, 2020Publication date: March 4, 2021Applicant: NXP USA, Inc.Inventors: Stefano Dal Toso, Mathieu Perin
-
Patent number: 9391214Abstract: A MOS varactor structure comprising a semiconductor body having a well region and a plurality of gate electrodes and a plurality of cathode electrodes arranged over the well region, wherein the gate electrodes comprise elongate pads, and the plurality of cathode contacts are connected by a cathode connection pattern, the cathode connection pattern comprising a plurality of arms, each of the plurality of arms arranged to extend over a part of a respective gate electrode pad.Type: GrantFiled: March 2, 2015Date of Patent: July 12, 2016Assignee: NXP B.V.Inventors: Olivier Tesson, Mathieu Perin, Laure Rolland du Roscoat
-
Publication number: 20150255630Abstract: A MOS varactor structure comprising a semiconductor body having a well region and a plurality of gate electrodes and a plurality of cathode electrodes arranged over the well region, wherein the gate electrodes comprise elongate pads, and the plurality of cathode contacts are connected by a cathode connection pattern, the cathode connection pattern comprising a plurality of arms, each of the plurality of arms arranged to extend over a part of a respective gate electrode pad.Type: ApplicationFiled: March 2, 2015Publication date: September 10, 2015Inventors: Olivier Tesson, Mathieu Perin, Laure Rolland du Roscoat